IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 a" />
參數(shù)資料
型號: IDT723672L12PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 23/29頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 16384X36 132QFP
標(biāo)準(zhǔn)包裝: 36
系列: 7200
功能: 同步
存儲容量: 576K(16K x 36)
數(shù)據(jù)速率: 83MHz
訪問時(shí)間: 12ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 723672L12PQF
3
COMMERCIALTEMPERATURERANGE
IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
PIN CONFIGURATION (CONTINUED)
TQFP (PN120-1, order code: PF)
TOP VIEW
5609 drw 03
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
FWFT
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
V
CC
GND
CLKA
ENA
W/
R
A
CSA FFA
/IRA
EFA
/ORA
V
CC
AFA AEA MBF2 MBA RST1 FS0 GND FS1 RST2 MBB MBF1 V
CC
AEB AFB EFB
/ORB
FFB
/IRB
GND
CSB W
/RB
ENB
CLKB
GND
A
11
A
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
31
32
33
34 35 36
37 38
39
40
41
42
43
44
45
46
47 48
49
50
51
52
53
54 55
56
57 58
59
60
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA and AEB) and a
programmable Almost-Full flag (
AFAandAFB). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFBindicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port
clockthatwritesdataintoitsarray.
EFA/ORA,EFB/ORB,AEAandAEBaretwo-
stage synchronized to the port clock that reads data from its array. Program-
mable offsets for
AEA,AEB, AFA and AFB areloaded byusingPortA.Three
default offset settings are also provided. The
AEA and AEB threshold can be
set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFB
threshold can be set at 8, 16 or 64 locations from the full boundary. All these
choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths. If,
at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT723652/723662/723672 are characterized for operation from 0
°C
to 70
°C.Industrialtemperaturerange(-40°Cto+85°C)isavailablebyspecial
order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
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