Figure 6. The Mechanism of Shifting Dat" />
參數(shù)資料
型號: IDT72401L15SO8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/9頁
文件大?。?/td> 0K
描述: IC FIFO PAR 64X4 15NS 16-SOIC
標準包裝: 1,000
系列: 7200
功能: 異步
存儲容量: 256(64 x 4)
數(shù)據(jù)速率: 15MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 16-SOIC
包裝: 帶卷 (TR)
其它名稱: 72401L15SO8
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
6
JUNE 29, 2012
Figure 6. The Mechanism of Shifting Data Out of the FIFO
NOTES:
1. OR HIGH indicates that data is available and a SO pulse may be applied.
2. SO goes HIGH causing the next step.
3. OR goes LOW.
4. The read pointer is incremented.
5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.
7. SO pulses applied when OR is LOW will be ignored.
Figure 5. Output TIming
STABLE DATA
SO
SI
IR
INPUT DATA
(2)
(3)
(1)
tIPH
tPT
(4)
(5)
2747 drw 08
tHIR
tSIR
NOTES:
1. FIFO is initially full.
2. SO pulse is applied.
3. SI is held HIGH.
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
SO
OR
OUTPUT DATA
A- DATA
(2)
(3)
(5)
2747 drw 10
(6)
(4)
(1)
(7)
A or B
B- DATA
SO
OR
OUTPUT DATA
tORL
2747 drw 09
1/fOUT
tSOH
tSOL
tODH
tORH
C-DATA
B-DATA
A-DATA
tODS
(2)
(1)
NOTES:
1. This data is loaded consecutively A, B, C.
2. Data is shifted out when SO makes a HIGH to LOW transition.
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