參數(shù)資料
型號(hào): IDT72401L25SO
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 0K
描述: IC FIFO PAR 64X4 25NS 16-SOIC
標(biāo)準(zhǔn)包裝: 46
系列: 7200
功能: 異步
存儲(chǔ)容量: 256(64 x 4)
數(shù)據(jù)速率: 25MHz
訪問(wèn)時(shí)間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
其它名稱: 72401L25SO
JUNE 2012
2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2747/13
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
IDT72401
IDT72403
CMOSPARALLELFIFO
64 x 4
FEATURES:
First-ln/First-Out Dual-Port memory
64 x 4 organization (IDT72401/72403)
RAM-based FIFO with low falI-through time
Low-power consumption
— Active: 175mW (typ.)
Maximum shift rate — 45MHz
High data output drive capability
Asynchronous and simultaneous read and write
Fully expandable by bit width
Fully expandable by word depth
IDT72403 have Output Enable pin to enable output data
High-speed data communications applications
High-performance CMOS technology
Available in CERDIP, plastic DIP and SOIC
Military product compliant to MlL-STD-883, Class B
Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
Green parts available, see ordering information
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous high-performance
First-ln/First-Outmemoriesorganized64wordsby4bits. TheIDT72403 also
hasanOutputEnable(OE)pin.TheFlFOsaccept4-bit dataatthedatainput
(D0-D3). The stored data stack up on a first-in/first-out basis.
AShiftOut(SO)signalcausesthedataatthenexttolastwordtobeshifted
totheoutputwhileallotherdatashiftsdownonelocationinthestack.TheInput
Ready (IR) signal acts like a flag to indicate when the input is ready for new
data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal
canalsobeusedtocascademultipledevicestogether.TheOutputReady(OR)
signal is a flag to indicate that the output remains valid data (OR = HIGH) or
to indicate that the FIFO is empty (OR = LOW). The OR can also be used to
cascademultipledevicestogether.
WidthexpansionisaccomplishedbylogicallyANDingtheIRandORsignals
toformcompositesignals.
Depthexpansionisaccomplishedbytyingthedatainputsofonedeviceto
the data outputs of the previous device. The IR pin of the receiving device is
connected to the SO pin of the sending device and the OR pin of the sending
device is connected to the Shift In (SI) pin of the receiving device.
Readingandwritingoperationsarecompletelyasynchronousallowingthe
FIFO to be used as a buffer between two digital machines of widely varying
operatingfrequencies.The45MHzspeedmakestheseFlFOsidealforhigh-
speed communicationandcontrollerapplications.
MilitarygradeproductismanufacturedincompliancewiththeofMIL-STD-
883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WRITE POINTER
INPUT
CONTROL
LOGIC
2747 drw01
SI
DATA IN
MASTER
RESET
WRITE MULTIPLEXER
MEMORY
ARRAY
READ POINTER
READ MULTIPLEXER
IR
D0-3
MR
OUTPUT
ENABLE
DATA IN
MASTER
RESET
SO
OR
Q0-3
OE
(IDT72403 only)
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