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參數(shù)資料
| 型號： | IDT72413L25DB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70 |
| 中文描述： | 64 X 5 OTHER FIFO, 20 ns, CDIP20 |
| 封裝： | 0.300 INCH, CERDIP-20 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 104K |
| 代理商： | IDT72413L25DB |
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.02
5
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2748 tbl 07
circuit
*Including scope and jig
DATA OUTPUT
Data is shifted out on the HIGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be ad-
vanced to the next word location. If data is present, valid data
will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, Output Ready will stay LOW
indicating the FIFO is empty. The last valid word read from the
FIFO will remain at the FlFOs output when it is empty. When
the FIFO is not empty Output Ready (OR) goes LOW on the
LOW-to-HlGH transition of Shift Out.
FALL-THROUGH MODE
The FIFO operates in a Fall-Through Mode when data gets
shifted into an empty FIFO. After the fall-through delay the
data propagates to the output. When the data reaches the
output, the Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is
completely full. When data is shifted out of the full FIFO a
location is available for new data. After a fall-through delay,
the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAM-
based FIFO (one clock cycle) is far less than the delay of a
Shift register-based FIFO.
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port
RAM architecture as opposed to the traditional shift register
approach. This FIFO architecture has a write pointer, a read
pointer and control logic, which allow simultaneous read and
write operations. The write pointer is incremented by the
falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
FIFO RESET
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FIFO to enter an empty
state signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (Q
0-4
)
will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In
(Sl). This loads input data into the first word location of the
FIFO and causes the lnput Ready to go LOW. On the HlGH-
to-LOW transition of Shift In, the write pointer is moved to the
next word position and Input Ready (lR) goes HlGH indicating
the readiness to accept new data. If the FIFO is full, Input
Ready will remain LOW until a word of data is shifted out.
RESISTOR VALUES FOR
STANDARD TEST LOAD
I
OL
24mA
12mA
8mA
R1
200
390
600
R2
300
760
1200
Figure 1. Output Load
2748 tbl 08
R1
30pF*
R2
5V
TEST POINT
2748 drw 03
or equivalent
2K
30pF*
5V
OUTPUT
STANDARD TEST LOAD
DESIGN TEST LOAD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72413L25P | High-Performance Current-Mode PWM Controller 8-SOIC 0 to 70 |
| IDT72413L25PB | High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70 |
| IDT72413L25SO | CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS |
| IDT72413L25SOB | High-Performance Current-Mode PWM Controller 8-PDIP 0 to 70 |
| IDT72413L35D | High-Performance Current-Mode PWM Controller 8-PDIP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72413L25P | 功能描述:IC FIFO PAR W/FLAGS 32KB 20DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72413L25SO | 功能描述:IC FIFO PAR W/FLAGS 32KB 20SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72413L25SO8 | 功能描述:IC FIFO PAR W/FLAGS 32KB 20SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72413L25SOG | 功能描述:IC FIFO PAR W/FLAGS 32KB 20SOIC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72413L25SOG8 | 功能描述:IC FIFO PAR W/FLAGS 32KB 20SOIC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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