參數(shù)資料
型號: IDT72413L35SO
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/10頁
文件大小: 0K
描述: IC FIFO PAR W/FLAGS 32KB 20SOIC
標準包裝: 37
系列: 7200
功能: 異步
存儲容量: 32K
訪問時間: 35ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 管件
其它名稱: 72413L35SO
1
DSC-2748/11
JUNE 2012
IDT72413
CMOS PARALLEL FIFO WITH FLAGS 64 x 5
2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
FEATURES:
First-ln/First-Out Dual-Port memory—45MHz
64 x 5 organization
Low-power consumption
— Active: 200mW (typical)
RAM-based internal structure allows for fast fall-through time
Asynchronous and simultaneous read and write
Expandable by bit width
Cascadable by word depth
Half-Full and Almost-Full/Empty status flags
High-speed data communications applications
Bidirectional and rate buffer applications
High-performance CMOS technology
Available in plastic DIP and SOIC
Green parts available, see ordering information
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads
andemptiesdataonafirst-in-first-outbasis. Itisexpandableinbitwidth.Allspeed
versions are cascad-able in depth.
TheFIFOhasaHalf-FullFlag,whichsignalswhenithas32ormorewords
in memory. The Almost-Full/Empty Flag is active when there are 56 or more
words in memory or when there are 8 or less words in memory.
ThisdeviceispinandfunctionallycompatibletotheMMI67413.Itoperates
atashiftrateof45MHz.Thismakesitidealforuseinhigh-speeddatabuffering
applications.ThisFIFOcanbeusedasaratebuffer,betweentwodigitalsystems
of varying data rates, in high-speed tape drivers, hard disk controllers, data
communicationscontrollersanDgraphicscontrollers.
TheIDT72413isfabricatedusinghigh-performanceCMOSprocess.This
processmaintainsthespeedandhighoutputdrivecapabilityofTTLcircuitsin
low-power CMOS.
FUNCTIONAL BLOCK DIAGRAM
2748 drw 01
DATA IN
FIFO
INPUT
STAGE
64 x 5
MEMORY
ARRAY
FIFO
OUTPUT
STAGE
INPUT
CONTROL
LOGIC
REGISTER
CONTROL
LOGIC
OUTPUT
CONTROL
LOGIC
FLAG
CONTROL
LOGIC
)
(MR)
MASTER
RESET
INPUT
READY
SHIFT
IN
(IR)
(SI)
DATA OUT
(Q0-4 )
SHIFT
OUT
OUPUT
READY
(SO)
(OR)
OUPUT ENABLE
(OE)
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
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