(Commercial: V
參數資料
型號: IDT72413L45P
廠商: IDT, Integrated Device Technology Inc
文件頁數: 4/10頁
文件大?。?/td> 0K
描述: IC FIFO PAR W/FLAGS 32KB 20DIP
標準包裝: 18
系列: 7200
功能: 異步
存儲容量: 32K
訪問時間: 45ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應商設備封裝: 20-PDIP
包裝: 管件
其它名稱: 72413L45P
3
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIALTEMPERATURERANGE
JUNE 29, 2012
OPERATING CONDITIONS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Commercial
IDT72413L45
IDT72413L35
IDT72413L25
Symbol
Parameter
Figure
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tSIH(1)
Shift in HIGH Time
2
9
9
16
ns
tSIL(1)
Shift in LOW TIme
2
11
17
20
ns
tIDS
InputDataSet-up
2
0
0
0
ns
tIDH
Input Data Hold Time
2
13
15
25
ns
tSOH(1)
Shift Out HIGH Time
5
9
9
16
ns
tSOL
Shift Out LOW Time
5
11
17
20
ns
tMRW
Master Reset Pulse
8
20
30
35
ns
tMRS
Master Reset Pulse to SI
8
20
35
35
ns
NOTE:
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1μF directly between VCC and GND with very short lead length is recommended.
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Commercial
IDT72413L45
IDT72413L35
IDT72413L25
Symbol
Parameter
Figure
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fIN
Shift In Rate
2
45
35
25
MHz
tIRL(1)
Shift In
↑ to Input Ready LOW
2
18
18
28
ns
tIRH(1)
Shift In
↓ to Input Ready HIGH
2
18
20
25
ns
fOUT
ShiftOutRate
5
45
35
25
MHz
tORL(1)
Shift Out
↓ to Output Ready LOW
5
18
18
28
ns
tORH(1)
Shift Out
↓ to Output Ready HIGH
5
19
20
25
ns
tODH(1)
Output Data Hold Previous Word
5
5
5
ns
tODS
Output Data Shift Next Word
5
19
20
20
ns
tPT
DataThroughputor"Fall-Through"
4, 7
25
28
40
ns
tMRORL
Master Reset
↓ to Output Ready LOW
8
25
28
30
ns
tMRIRH(3)
Master Reset
↑ to Input Ready HIGH
8
25
28
30
ns
tMRIRL(2)
Master Reset
↓ to Input Ready LOW
8
25
28
30
ns
tMRQ
Master Reset
↓ toOutputsLOW
8
20
25
35
ns
tMRHF
Master Reset
↓ to Half-Full Flag
8
25
28
40
ns
tMRAFE
Master Reset
↓ to AF/E Flag
8
25
28
40
ns
tIPH(3)
Input Ready Pulse HIGH
4
5
5
5
ns
tOPH(3)
Output Ready Pulse HIGH
7
5
5
5
ns
tORD(3)
Output Ready
↑ HIGH to Valid Data
5
5
5
7
ns
tAEH
Shift Out
↑ to AF/E HIGH
9
28
28
40
ns
tAEL
Shift In
↑ to AF/E
9
28
28
40
ns
tAFL
Shift Out
↑ to AF/E LOW
10
28
28
40
ns
tAFH
Shift In
↑ to AF/E HIGH
10
28
28
40
ns
tHFH
Shift In
↑ to HF HIGH
11
28
28
40
ns
tHFL
Shift Out
↑ to HF LOW
11
28
28
40
ns
tPHZ(3)
Output Disable Delay
12
12
12
15
ns
tPLZ(3)
12
12
12
15
tPLZ(3)
Output Enable Delay
12
15
15
20
ns
tPHZ(3)
12
15
15
20
NOTES:
1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1μF directly between VCC and GND with very short lead length is recommended.
2. If the FIFO is full, (IR = HIGH), MR
↑ forces IR to go LOW, and MR ↓ causes IR to go HIGH.
3. Guaranteed by design but not currently tested.
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