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參數(shù)資料
| 型號(hào)： | IDT72421L50LB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9 |
| 中文描述： | 64 X 9 OTHER FIFO, 25 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 214K |
| 代理商： | IDT72421L50LB |
5.07
2
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
PIN DESCRIPTIONS
Symbol
D
0
-D
8
Data Inputs
RS
Reset
Name
I/O
I
I
Description
Data inputs for a 9-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after
power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
If the FIFO is configured to have programmable flags,
WEN1
is the only write enable pin.
When
WEN1
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables,
WEN1
must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the
FF
is LOW.
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD
is HIGH at reset, this pin operates as a second write enable. If WEN2/
LD
is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,
WEN1
must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the
FF
is LOW. If the FIFO is config-
ured to have programmable flags, WEN2/
LD
is held LOW to write or read the programmable flag
offsets.
Data outputs for a 9-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1
and
REN2
are
asserted.
When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF
is LOW.
When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a
high-impedance state.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7.
PAE
is synchronized to RCLK.
WCLK
Write Clock
I
WEN1
Write Enable 1
I
WEN2/
LD
Write Enable 2/
Load
I
Q
0
-Q
8
RCLK
Data Outputs
Read Clock
O
I
REN1
Read Enable 1
I
REN2
Read Enable 2
I
OE
Output Enable
I
EF
Empty Flag
O
PAE
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
Full Flag
O
PAF
O
When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7.
PAF
is synchronized to WCLK.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is
HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
FF
O
V
CC
GND
Power
Ground
2655 tbl 01
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
7
Q
Q
5
6
7
8
9
10
11
12
13
CC
8
6
5
1
D
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
27
26
25
24
23
22
21
29
28
4
3
2
1
32 31 30
14 15 16 17 18 19 20
D
D
D
D
D
2
3
4
5
6
D
D
7
8
3
Q
4
Q
2
Q
1
Q
0
Q
F
E
J32-1
L32-1
INDEX
2655 drw 02
TQFP
TOP VIEW
LCC/PLCC
TOP VIEW
R
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
5
5
6
7
8
16
CC
8
7
6
1
D
D
0
PAF
PAE
GND
REN1
RCLK
REN2
27 26 25
24
23
22
21
20
19
18
17
29 28
32 31 30
9 10 11 12 13 14 15
D
2
D
3
D
4
D
5
D
6
D
7
D
8
4
Q
2655 drw 02a
Q
Q
3
2
1
Q
0
Q
E
O
F
1
2
3
4
PR32-1
INDEX
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