參數(shù)資料
型號(hào)： IDT72510L25J
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： Current-Mode PWM Controller 8-PDIP 0 to 70
中文描述： 512 X 18 BI-DIRECTIONAL FIFO, 25 ns, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 15/32頁
文件大小： 440K
代理商： IDT72510L25J
5.31
15
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION REGISTER 7 FORMAT
BIT
0-7
8
FUNCTION
Unused
Parity Input Control
B
→
A
Parity Output Control
A
→
B
Parity Odd/Even
Control
Assign Parity Error to
0
Disable Parity Generate, Enable Parity Check
1
0
1
Enable Parity Generate, Disable Parity Check
Disable Parity Generate, Enable Parity Check
Enable Parity Generate, Disable Parity Check
9
10
0
1
0
Odd
Even
No Parity Error Output
11
Flag A Pin
Unused
1
Parity Error on Flag A Pin
12-15
Number of Words in FIFO
From
0
To
0
Empty Flag
Asserted
Almost-Empty Flag
Asserted
Almost-Full Flag
Not Asserted
Full Flag
Not Asserted
1
n
Not Asserted
Asserted
Not Asserted
Not Asserted
n + 1
D - (m + 1)
Not Asserted
Not Asserted
Not Asserted
Not Asserted
D - m
D
D - 1
D
Not Asserted
Not Asserted
Not Asserted
Not Asserted
Asserted
Asserted
Not Asserted
Asserted
NOTE:
1. BiFIFO flags can be assigned to external flag pins to be observed. D = FIFO depth (IDT72510 = 512, IDT72520 = 1024),
n = Almost-Empty flag offset, m = Almost-Full flag offset.
2669 tbl 17
Table 13. Internal Flag Truth Table.
INTERNAL FLAG TRUTH TABLE
assertion. After 2 to 5 internal clocks, ACK is asserted by the
BiFIFO. ACK will not be asserted if a read is attempted on an
Empty A
→
B FIFO or if a write is attempted on a Full B
→
A FIFO.
If the BiFIFO is in Motorola-style interface mode, R/
W
B
is set
at the same time that ACK is asserted. One internal clock later,
DS
B
is asserted. If the BiFIFO is in Intel-style interface mode,
either
R
B
or
W
B
is asserted one internal clock after ACK
assertion. These read/write controls stay asserted for 1 or 2
internal clocks, then ACK,
DS
B
,
R
B
and
W
B
are made inactive.
This completes the transfer of one 9-bit word.
On the next rising edge of CLK, REQ is sampled. If REQ is
still asserted, another DMA transfer starts with the assertion
of ACK. Data transfers will continue as long as REQ is
asserted.
Parity Checking and Generation
Parity generation or checking is performed by the BiFIFO
on data passing through Port B. Parity can either be odd or
even as determined by Bit 10 of Configuration Register 7.
When parity checking is enabled, D
B8
is treated as a data
bit. D
B8
data will be passed to D
A16
(bypass operation) or stored
in the RAM array (FIFO operation) for B->A operation; similarly,
D
A16
or parity bits from the RAM array will be passed to D
B8
for A->B operations. A->B read parity errors and B->A write
parity errors are shown in Bit 9 and 10 in the Status Register.
If an external parity error signal is required, a logical OR of the
bits go to the LSB (D
A0
-D
A7
, D
A16
) or the MSB (D
A8
-D
A15
, D
A17
)
of Port A. This data ordering is controlled by bit 1 of Configu-
ration Register 5 (see Table 11).
DMA Control Interface
The BiFIFO has DMA control to simplify data transfers with
peripherals. For the BiFIFO DMA controls (REQ, ACK and
CLK) to operate, the BiFIFO must be in peripheral interface
mode (Configuration Register 5, Table 11).
DMA timing is controlled by the external clock input, CLK.
An internal clock is derived from this CLK signal to generate
the
R
B
,
W
B
,
DS
B
and R/
W
B
output signals. The internal clock
also determines the timing between REQ assertion and ACK
assertion. Bit 9 of Configuration Register 5 determines whether
the internal clock is the same as CLK or whether the internal
clock is CLK divided by 2.
Bit 8 of Configuration Register 5 sets whether
R
B
,
W
B
and
DS
B
are asserted for 1 or 2 internal clocks. Bits 6 and 7 of
Configuration Register 5 set the number of clocks between
REQ assertion and ACK assertion. The clocks between REQ
assertion and ACK assertion can be 2, 3, 4 or 5.
Bits 4 and 5 of Configuration Register 5 set the polarity of
the REQ and ACK pins, respectively.
A DMA transfer command sets the Port B read/write direc-
tion (see Table 5). The timing diagram for DMA transfers is
shown in Figure 17. The basic DMA transfer starts with REQ
2669 tbl 16
Table 12. BiFIFO Configuration Register 7 Format
相關(guān)PDF資料
PDF描述
IDT72510L35J Current-Mode PWM Controller 8-PDIP 0 to 70
IDT72510L50J High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70
IDT72520 BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
IDT72520L25J BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
IDT72520L35J BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72510L35J 制造商:Integrated Device Technology Inc 功能描述:
IDT72605L20J 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72605L20J8 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72605L20PF 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72605L20PF8 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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