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參數(shù)資料
| 型號： | IDT72510L50J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70 |
| 中文描述： | 512 X 18 BI-DIRECTIONAL FIFO, 50 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 440K |
| 代理商： | IDT72510L50J |
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5.31
16
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
two parity error bits is brought out to FLG
A
pin by setting Bit 11
of Configuration Register 7.
Parity generation creates the ninth bit. This ninth bit is
placed on D
B8
for A->B read operation, and on D
A16
or RAM
array for B->A write operation.
It is recommended that if the parity pins (D
B8
, D
A16
, and D
A17
)
are not used, they should be pulled down with 10K resistors
for noise immunity.
Intelligent Reread/Rewrite
Intelligent reread/rewrite is a method the BiFIFO uses to
help assure data integrity. Port B of the BiFIFO has two extra
pointers, the Reread Pointer and the Rewrite Pointer. The
Reread Pointer is associated with the A->B FIFO Read
Pointer, while the Rewrite Pointer is associated with the B->A
FIFO Write Pointer. The Reread Pointer holds the start ad-
dress of a data block in the A->B FIFO RAM, and the Read
Pointer is the current address of the same FIFO RAM array.
By loading the Read Pointer with the value held in the Reread
Pointer (RER asserted), reads will start over at the beginning
of the data block. In order to mark the beginning of a data
block, the Reread Pointer should be loaded with the Read
Pointer value (LDRER asserted) before the first read is
performed on this data block. Figure 6 shows a Reread
operation.
Similarly, the Rewrite Pointer holds the start address of a
data block in the B->A FIFO RAM, while the Write Pointer is
the current address within the RAM array. The operation of the
REW and LDREW is identical to the RER and LDRER dis-
cussed above. Figure 7 shows a Rewrite operation.
For the reread data protection, Bit 2 of Configuration
Register 5 can be set to 1 to prevent the data block form being
overwritten. In this way, the assertion of A->B full flag will occur
when the write pointer meets the reread pointer instead of the
read pointer as in the normal definition. For the rewrite data
protection, Bit 3 of Configuration Register 5 can be set to 1 to
prevent the data block from being read. In this case, the
assertion of B->A empty flag will occur when the read pointer
meets the rewrite pointer instead of the write pointer.
In conclusion, Bit 2 and 3 of Configuration Register 5 are
used to redefine Full & Empty flags for data block partition.
Although it can serve the purpose of data protection, the
setting of these 2 bits is independent of the functions caused
by RER/REW, or LDRER/LDREW assertions.
REWRITE OPERATIONS
(3,4)
REREAD OPERATIONS
(1,2)
2669 drw 08
2669 drw 09
NOTES:
1. If bit 2 is set to 1,
Empty flag asserted if Read = Write
Full flag asserted if Reread + FIFO size = Write
2. If bit 2 is set to 0,
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size = Write
NOTES:
1. If bit 3 is set to 1,
Empty flag asserted if Read = Rewrite
Full flag asserted if Read + FIFO size = Write
2. If bit 3 is set to 0,
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size = Write
Write
Pointer
Read
Pointer
Rewrite
Pointer
B
→
A
FIFO
Rewrite
function
Load Rewrite
function
Figure 7. BiFIFO Rewrite Operations
Figure 6. BiFIFO Reread Operations
Write
Pointer
Reread
Pointer
Read
Pointer
A
→
B
FIFO
Reread
function
Load
Reread
function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72520 | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72520L25J | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72520L35J | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72520L50J | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72510 | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
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參數(shù)描述 |
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| IDT72605L20J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L20PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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