參數(shù)資料
型號: IDT72511L35GB
廠商: Integrated Device Technology, Inc.
英文描述: High-Performance Current-Mode PWM Controller 8-SOIC 0 to 70
中文描述: 雙向并行FIFO的512 × 18
文件頁數(shù): 13/28頁
文件大小: 434K
代理商: IDT72511L35GB
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.32
13
prevent the data block from being read. In this case the
assertion of B->A empty flag will occur when the read pointer
meets the rewrite pointer instead of the write pointer.
In conclusion, Bit 2 and 3 of Configuration Register 5 are
used to redefine Full & Empty flags for data block partition.
Although it can serve the purpose of data protection, the
setting of these 2 bits is independent of the functions caused
by RER/REW, or LDRER/LDREW assertions.
Programmable Input/Output
The BiFlFO has six programmable I/0 pins (PlO
0
- PIO
5
)
which are controlled by Port A through Configuration Regis-
ters 6 and 7. Data from the programmable I/O pins is mapped
directly to the six least significant bits of Configuration Regis-
ter 6. Figure 4 shows the format of Configuration Register 6.
This data is read or written by Port A on the data pins
(DA
0
- DA
5
). A programmed output PIO
i
pin (i = 0, 1, . . . , 5)
displays the data latched in Bit i of Configuration Register 6.
A programmed input PIO
i
pin allows Port A bus to sample its
data on D
Ai
by reading Configuration Register 6. The read and
write timing for the programmable I/O pins is shown in Figure
19. The direction of each programmable I/O pin can be set
independently by programming the mask in Configuration
Register 7. Each P10 pin has a corresponding input/output
direction mask bit in Configuration Register 7. Figure 5 shows
the format of Configuration Register 7. Setting a mask bit to a
logic 1 makes the corresponding I/O pin an output. Mask bits
set to logic 0 force the corresponding I/O pin to an input.
REWRITE OPERATIONS
(3,4)
REREAD OPERATIONS
(1,2)
2668 drw 08
NOTES:
1. If bit 2 is set to 1,
Empty flag asserted if Read = Write
Full flag asserted if Reread + FIFO size = Write
2. If bit 2 is set to 0,
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size = Write
NOTES:
1. If bit 3 is set to 1,
Empty flag asserted if Read = Rewrite
Full flag asserted if Read + FIFO size = Write
2. If bit 3 is set to 0,
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size = Write
Write
Pointer
Read
Pointer
Rewrite
Pointer
B
A
FIFO
Rewrite
function
Load Rewrite
function
Figure 7. BiFIFO Rewrite Operations
Figure 6. BiFIFO Reread Operations
Write
Pointer
Reread
Pointer
Read
Pointer
A
B
FIFO
Reread
function
Load
Reread
function
2668 drw 09
相關(guān)PDF資料
PDF描述
IDT72511L35J High-Performance Current-Mode PWM Controller 8-PDIP 0 to 70
IDT72511L35JB High-Performance Current-Mode PWM Controller 8-PDIP 0 to 70
IDT72511L40JB PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
IDT72511L50G PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
IDT72511L50GB PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
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