參數(shù)資料
型號(hào)： IDT72511L35JB
廠商： Integrated Device Technology, Inc.
英文描述： High-Performance Current-Mode PWM Controller 8-PDIP 0 to 70
中文描述： 雙向并行FIFO的512 × 18
文件頁(yè)數(shù)： 8/28頁(yè)
文件大?。?/td> 434K
代理商： IDT72511L35JB
5.32
8
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
request DMA circuitry can also be reset independently. A
software Reset All command resets all the pointers, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is
NOT
the
same as a software Reset All command. Table 6 shows the
BiFIFO state after the different hardware and software resets
Status Register
The Status Register reports the state of the programmable
flags and the DMA read/write direction. The Status Register
is read by setting
CS
A
= 0, A
1
= 1, A
0
= 1 (see Table 1). See
Table 7 for the Status Register format.
Configuration Registers
The eight Configuration Register formats are shown in
RESET COMMAND FUNCTIONS
2668 tbl 04
Table 3. Reset Command Functions
DMA DIRECTION COMMAND FUNCTIONS
Operands
XX0
Function
Write B
→
A FIFO
Read A
→
B FIFO
XX1
Reset
Operands
000
Function
No Operation
Reset B
→
A FIFO (Read, Write, and Rewrite
Pointers = 0)
Reset A
→
B FIFO (Read, Write, and Reread
Pointers = 0)
Reset B
→
A and A
→
B FIFO
001
010
011
100
Reset Internal DMA Request Circuitry
101
110
No Operation
No Operation
111
Reset All
Reset
The IDT72511 and IDT72521 have a hardware reset pin
(
RS
) that resets all BiFIFO functions. A hardware reset re-
quires the following four conditions:
R
B
and
W
B
must be HIGH,
RER
and
REW
must be HIGH, LDRER and LDREW must be
LOW, and
DS
A
must be HIGH (Figure 9). After a hardware
reset, the BiFIFO is in the following state: Configuration
Registers 0-3 are
0000H
, Configuration Register 4 is set to
6420H
, and Configuration Registers 5, 6 and 7 are
0000H
.
Additionally, all the pointers including the Reread and Rewrite
Pointers are set to
0
, the DMA direction is set to B
→
A write,
and the internal DMA request circuitry is cleared (set to its
initial state).
A software reset command can reset A
→
B pointers and the
B
→
A pointers to
0
independently or together. The internal
CS
A
0
A
1
0
A
0
0
Read
Write
B
→
A FIFO
A
→
B FIFO
0
0
0
1
1
0
9-bit Bypass Path
Configuration
Registers
9-bit Bypass Path
Configuration
Registers
0
1
1
Status Register
Command
Register
1
X
X
Disabled
Disabled
PORT A RESOURCE SELECTION
2668 tbl 03
Table 1. Accessing Port A Resources Using
CS
A
, A
0
and A
1
Command
Opcode
Function
0000
0001
Reset BiFIFO (see Table 3)
Select Configuration Register (see Table 4)
0010
0011
0100
Load Reread Pointer with Read Pointer Value
Load Rewrite Pointer with Write Pointer Value
Load Read Pointer with Reread Pointer Value
0101
0110
0111
Load Write Pointer with Rewrite Pointer Value
Set DMA Transfer Direction (see Table 5)
Reserved
Increment A
→
B FIFO Read Pointer (Port B)
Increment B
→
A FIFO Write Pointer (Port B)
1000
1001
1010
1011
Reserved
Reserved
COMMAND OPERATIONS
2668 tbl 07
Table 5. Set DMA Direction Command Functions. Command Only
Operates in Peripheral Interface Mode
Operands
000
001
010
Function
Select Configuration Register 0
Select Configuration Register 1
Select Configuration Register 2
011
100
101
110
111
Select Configuration Register 3
Select Configuration Register 4
Select Configuration Register 5
Select Configuration Register 6
Select Configuration Register 7
SELECT CONFIGURATION REGISTER/
COMMAND FUNCTIONS
2668 tbl 06
Table 4. Select Configuration Register Functions.
2668 tbl 05
Table 2. Functions Performed by Port A Commands
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