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參數(shù)資料
| 型號： | IDT72521L25J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18 |
| 中文描述： | 1K X 18 BI-DIRECTIONAL FIFO, 25 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 434K |
| 代理商： | IDT72521L25J |
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IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.32
3
PIN DESCRIPTION
2668 tbl 01
Symbol
Name
I/O
Description
D
A0-
D
A17
Data A
I/O
Data inputs and outputs for the 18-bit Port A bus.
CS
A
Chip Select A
I
Port A is accessed when Chip Select A is LOW.
DS
A
Data Strobe
A
Read/Write A
I
Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is
read out of Port A on the falling edge of Data Strobe when Chip Select is LOW.
This pin controls the read or write direction of Port A. When
CS
A
is LOW and R/
W
A
is HIGH,
data is read from Port A on the falling edge of
DS
A
. When
CS
A
is LOW and R/
W
A
is LOW, data
is written into Port A on the rising edge of
DS
A
.
When Chip Select A is asserted, A
0
, A
1
, and Read/Write A are used to select one of six internal
resources.
Data inputs and outputs for the 18-bit Port B bus.
R/
W
A
I
A
0
, A
1
Addresses
I
D
B0
-D
B17
Data B
I/O
R
B
(
DS
B)
Read B
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is
programmed to peripheral mode this pin functions as an output. This pin can function as part of
an Intel-style interface (
R
B
) or as part of a Motorola-style interface (
DS
B
). As an Intel-style
interface, data is read from Port B on a falling edge of
R
B.
As a Motorola-style interface, data is
read on the falling edge of
DS
B
or written on the rising edge of
DS
B
through Port B. The default
is Intel-style processor mode. (
R
B
as an input).
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is
programmed to peripheral mode this pin functions as an output. This pin can function as part of
an Intel-style interface (
W
B
) or as part of a Motorola-style interface (R/
W
B
). As an Intel-style
interface, data is written to Port B on a rising edge of
W
B
. As a Motorola-style interface, data is
read (R/
W
B
= HIGH) or written (R/
W
B
= LOW) to Port B in conjunction with a Data Strobe B
falling or rising edge. The default is Intel-style processor mode (
W
B
as an input.)
Loads A
→
B FIFO Read Pointer with the value of the Reread Pointer when LOW.
W
B
(R/
W
B)
Write B
RER
Reread
I
REW
Rewrite
I
Loads B
→
A FIFO Write Pointer with the value of the Rewrite Pointer when LOW.
LDRER
Load Reread
I
Loads the Reread Pointer with the value of the A
→
B FIFO Read Pointer when HIGH.
LDREW
Load Rewrite
I
Loads the Rewrite Pointer with the value of the B
→
A FIFO Write Pointer when HIGH.
REQ
Request
I
When Port B is programmed in peripheral mode, asserting this pin begins a data transfer.
Request can be programmed either active HIGH or active LOW.
ACK
Acknowledge
O
When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a
Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed
either active HIGH or active LOW.
CLK
Clock
I
This pin is used to generate timing for ACK,
R
B
,
W
B
,
DS
B
and R/
W
B
when Port B is in the
peripheral mode.
FLG
A
-
FLG
D
Flags
O
These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each
of the two internal FIFOs (A
→
B and B
→
A) has four internal flags: Empty, Almost-Empty,
Almost-Full and Full.
Six general purpose I/O pins. The input or output direction of each pin can be set independently.
PIO
0
-PIO
5
Program-
mable Inputs/
Outputs
Reset
I/O
RS
I
A LOW on this pin will perform a reset of all BiFIFO functions.
V
CC
Power
There are two +5V power pins.
GND
Ground
There are five Ground pins at 0V.
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| IDT72521L35JB | PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72605L20J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L20PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L25J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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