canbewrittenorreadinPortB.IfR/W
參數(shù)資料
型號(hào): IDT72605L25J8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 16/17頁(yè)
文件大?。?/td> 0K
描述: IC FIFO BI SYNC 256X18 68-PLCC
標(biāo)準(zhǔn)包裝: 250
系列: 7200
功能: 同步
存儲(chǔ)容量: 9.2K(512 x 18)
數(shù)據(jù)速率: 40MHz
訪問(wèn)時(shí)間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24x24)
包裝: 帶卷 (TR)
其它名稱(chēng): 72605L25J8
8
INDUSTRIALTEMPERATURERANGE
IDT72605/72615 CMOS SYNCBiFIFO
256 x 18x 2 and 512 x 18 x 2
canbewrittenorreadinPortB.IfR/WBandENB areLOW,dataiswritteninto
inputregister,andonLOW-to-HIGHtransitionofCLKBdataiswrittenintoinput
registerandtheFIFOmemory. IfR/WBisHIGHandOEBisLOW,datacomes
outofbusandisreadfromoutputregisterintothree-statebuffer.Inbypassmode,
ifR/WBisLOW,bypassmessagesaretransferredintoB
→Aoutputregister.
IfR/WAisHIGH,bypassmessagesaretransferredintoA
→Boutputregister.
Refertopindescriptionsformoreinformation.
TABLE 3 FLAG OFFSET REGISTER FORMAT
NOTE:
1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
17
16
15
14
13
12
11
10
9876543210
PAEAB
Register
XXXXXXXXX
A
→B FIFO Almost-Empty Flag Offset
17
16
15
14
13
12
11
10
9876543210
PAFAB Register
XXXXXXXXX
A
→B FIFO Almost-Full Flag Offset
17
16
15
14
13
12
11
10
9876543210
PAEBA
Register
XXXXXXXXX
B
→A FIFO Almost-Empty Flag Offset
17
16
15
14
13
12
11
10
9876543210
PAFBA Register
XXXXXXXXX
B
→A FIFO Almost-Full Flag Offset
TABLE 4 INTERNAL FLAG TRUTH TABLE
Number of Words
in FIFO
From
To
EF
PAE
PAF
FF
0
LOW
HIGH
1
n
HIGH
LOW
HIGH
n+1
D-(m+1)
HIGH
D-m
D-1
HIGH
LOW
HIGH
D
HIGH
LOW
NOTE:
1. n = Programmable Empty Offset (PAEAB Register or PAEBA Register)
m = Programmable Full Offset (PAFAB Register or PAFBA Register)
D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
TABLE 5 PORT B OPERATION CONTROL SIGNALS
Data B
R/WB
ENB
OEB
I/O
Port B Operation
000
I
Data B is written on CLKB
↑. This write cycle immediately following output low-impedance cycle is prohibited. Note
that even though OEB = 0, a LOW logic level on R/WB, once qualified by a rising edge on CLKB, will put Data B into a high-
impedance state.
0
1
I
Data B is written on CLKB
↑.
0
1
X
I
Data B is ignored
1
0
O
Data is read(1)from RAM array to output register on CLKB
≠ Data B is low-impedance
1
0
1
O
Data is read(1) from RAM array to output register on CLKB
≠, Data B is high- impedance
1
0
O
Outputregisterdoesnotchange(2),DataBislow-impedance
1
O
Outputregisterdoesnotchange(2),DataBishigh-impedance
NOTES:
1. When A2A1A0 = 000 or 1XX, the next A
→B FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and
bypass data is read from the Port B output register.
2. Regardless of the condition of A2A1A0, the data in the Port B output register does not change and the A
→B read pointer does not advance.
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