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參數(shù)資料
| 型號： | IDT72605L35J8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO BI SYNC 256X18 68-PLCC |
| 標準包裝： | 250 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 9.2K（512 x 18） |
| 訪問時間： | 35ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（24x24） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72605L35J8 |
6
INDUSTRIALTEMPERATURERANGE
IDT72605/72615 CMOS SYNCBiFIFO
256 x 18x 2 and 512 x 18 x 2
CLK
DATA
ADDR, I/0
CONTROL
LOGIC
RAM A
IDT
SYNCBIFIFO
DATA B
CONTROL B
SYSTEM
CLOCK A
CONTROL
LOGIC
CLK
MICROPROCESSOR
A
MICROPROCESSOR
B
DATA
ADDR, I/0
RAM B
SYSTEM
CLOCK B
IDT
SYNCBIFIFO
DATA B
CLKB
CONTROL B
DATA A
CLKA
CONTROL A
DATA A
CONTROL A
2704 drw 05
CLKB
CLKA
FUNCTIONALDESCRIPTION
IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral
applications. Datacanbestoredorretrievedfromtwosourcessimultaneously.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Two Dual-Port FIFO memory arrays are contained in the
SyncBiFIFO; one data buffer for each direction. Each port has its own
independentclock.DatatransferstotheI/Oregistersaregatedbytheenable
signals. The transfer direction for each port is controlled independently by a
read/writesignal. IndividualoutputenablesignalscontrolwhethertheSyncBiFIFO
is driving the data lines of a port or whether those data lines are in a high-
impedancestate.TheprocessorconnectedtoPortAoftheBiFIFOcansend
orreceivemessagesdirectlytothePortBdeviceusingthe18-bitbypasspath.
The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit
configuration, two SyncBiFIFOs operate in parallel. Both devices are pro-
grammedsimultaneously, 18databitstoeachdevice. Thisconfigurationcan
beextendedtowiderbuswidths(54-to54-bits,72-to72-bits,etc.)byadding
moreSyncBiFIFOstotheconfiguration.Figure1showsmultipleSyncBiFIFOs
configuredfor multiprocessorcommunication.
The microprocessor or microcontroller connected to Port A controls all
operationsoftheSyncBiFIFO.Thus,allPortAinterfacepinsareinputsdriven
by the controlling processor. Port B interfaces with a second processor. The
Port B control pins are inputs driven by the second processor.
RESET
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate
with CSA, ENA and ENB HIGH. During reset, both internal read and write
pointersaresettothefirstlocation.Aresetisrequiredafterpowerupbeforea
writeoperationcantakeplace.TheA
→BandB→AFIFOEmptyFlags(EFAB,
EFBA)andProgrammableAlmost-Emptyflags(PAEAB, PAEBA)willbesetto
LOW after tRSF. The A
→B and B→A FIFO Full Flags (FFAB, FFBA) and
ProgrammableAlmost-Fullflags(PAFAB,PAFBA)willbesettoHIGHaftertRSF.
Afterthereset,theoffsetsoftheAlmost-EmptyflagsandAlmost-Fullflagsforthe
A
→BandB→AFIFOoffsetdefaultto8.
PORT A INTERFACE
The SyncBiFIFO is straightforward to use in micro-processor-based
systemsbecauseeachporthasastandardmicroprocessorcontrolset.PortA
interfaceswithmicroprocessorthroughthethreeaddresspins(A2-A0)anda
Chip Select CSA pins. When CSA is asserted, A2,A1,A0 and R/WA are used
to select one of six internal resources (Table 1).
WithA2=0andA1=0,A0determineswhetherdatacanbereadoutofoutput
register or be written into the FIFO (A0=0), or the data can pass through the
FIFO through the bypass path (A0=1).
WithA2=1,fourprogrammableflags(twoA
→BFIFOprogrammableflags
and two B
→A FIFO programmable flags) can be selected: the A→B FIFO
Almost-Empty flag Offset (A1=0, A0=0), A
→B FIFO Almost-Full flag Offset
(A1=0,A0=1),B
→AFIFOAlmost-EmptyflagOffset(A1=1,A0=0),B→AFIFO
Almost-FullflagOffset(A1=1,A0=1).
PortAisdisabledwhenCSAisdeassertedanddataAisinhigh-impedance
state.
BYPASSPATH
ThebypasspathsprovidedirectcommunicationbetweenPortAandPort
B.Therearetwofull18-bitbypasspaths,oneineachdirection.Duringabypass
operation,dataispasseddirectlybetweentheinputandoutputregisters,and
the FIFO memory is undisturbed.
PortAinitiatesandterminatesallbypassoperations. Thebypassflag,BYPB,
isassertedtoinformPortBthatabypassoperationisbeginning.Thebypass
flag state is controlled by the Port A controls, although the BYPB signal is
synchronizedtoCLKB.So,BYPBisassertedonthenextrisingedgeofCLKB
whenA2A1A0=001andCSAisLOW. WhenPortAreturnstonormalFIFOmode
(A2A1A0=000 or CSA is HIGH), BYPB is deasserted on the next CLKB rising
edge.
OncetheSyncBiFIFOisinbypassmode,alldatatransfersarecontrolled
by the standard Port A (R/WA, CLKA, ENA, OEA) and Port B (R/WB, CLKB,
ENB,OEB)interfacepins. Eachbypasspathcanbeconsideredasaoneword
deepFIFO.Dataisheldineachinputregisteruntilitisread. Sincethecontrols
Figure 1. 36- to 36-bit Processor Interface Configuration
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A consists of R/WA, ENA, OEA, CSA, A2, A1, A0. Control B consists of R/WB, ENB, OEB.
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| IDT72605L50J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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