COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
12
JANUARY 13, 2009
Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)
Figure 5. Reset Timing(2)
RS
REN, WEN, LD
PAE
PAF, WXO/
HF, RXO
tRSR
Q0 - Q17
OE = 0
OE = 1
(1)
3139 drw 05
tRSS
CONFIGURATION SETTING
tRSR
FL, RXI, WXI
RCLK, WCLK
FF/IR
tRSF
EF/OR
FWFT Mode
IDT Standard Mode
(3)
(2)
tRSF
tRS
WCLK
D0 - D17
WEN
FF
tCLK
tCLKH
tCLKL
tDS
tENS
tDH
tENH
tWFF
DATA IN VALID
NO OPERATION
RCLK
tSKEW1(1)
REN
3139 drw 06
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then
FF may not change state until the next WCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. Single device mode (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if
OE = 0 and tri-state if OE = 1.