IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9," />
參數(shù)資料
型號: IDT72821L10TF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC FIFO SYNC DUAL 1024X9 64QFP
標準包裝: 80
系列: 7200
功能: 同步
存儲容量: 9K(1K x 9)
數(shù)據(jù)速率: 100MHz
訪問時間: 10ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72821L10TF
8
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
NUMBER OF WORDS IN ARRAY A
FFA
PAFA
PAEA
EFA
NUMBER OF WORDS IN ARRAY B
FFB
PAFB
PAEB
EFB
72801
72811
72821
00
0
H
L
1 to n(1)
HH
L
H
(n+1) to (256-(m+1))
(n+1) to (512-(m+1))
(n+1) to (1,024-(m+1))
H
(256-m)(2) to 255
(512-m)(2) to 511
(1,024-m)(2) to 1,023
H
L
H
256
512
1,024
L
H
NUMBER OF WORDS IN ARRAY A
FFA
PAFA
PAEA
EFA
NUMBER OF WORDS IN ARRAY B
FFB
PAFB
PAEB
EFB
72831
72841
72851
00
0
H
L
1 to n(1)
HH
L
H
(n+1) to (2,048-(m+1))
(n+1) to (4,096-(m+1))
(n+1) to (8,192-(m+1))
H
(2,048-m)(2) to 2,047
(4,096-m)(2) to 4,095
(8,192-m)(2) to 8,191
H
L
H
2,048
4,096
8,192
L
H
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will
goLOWwhentheamountofdatainArrayA(B)reachesthealmost-fullcondition.
IfnoreadsareperformedafterReset,PAFA(PAFB)willgoLOWafter(256-m)
writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO
A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the
IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or
(8,192-m) writes to the IDT72851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe
Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
registers.
IfthereisnoFulloffsetspecified,PAFA(PAFB)willgoLOWatFull-7words.
PAFA(PAFB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
ofWCLKA(WCLKB).
ProgrammableAlmost–EmptyFlag(PAEA,PAEB)—PAEA(PAEB)will
goLOWwhenthereadpointeris"n+1"locationslessthanthewritepointer. The
offset"n"isdefinedintheEmptyOffset registers. Ifnoreadsareperformedafter
Reset,PAEA(PAEB)willgoHIGHafter"n+1"writestoFIFOA(B).
IfthereisnoEmptyoffsetspecified,PAEA(PAEB)willgoLOWatEmpty+7
words.
PAEA(PAEB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
of the Read Clock RCLKA (RCLKB).
Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data
outputs for memory array A, QB0 - QB8are the nine data outputs for memory
array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
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