IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9" />
參數(shù)資料
型號(hào): IDT72821L25TF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/16頁
文件大?。?/td> 0K
描述: IC FIFO SYNC DUAL 1024X9 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 7200
功能: 同步
存儲(chǔ)容量: 9K(1K x 9)
數(shù)據(jù)速率: 40MHz
訪問時(shí)間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72821L25TF8
14
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
Device Configuration, the Read Enable 2 RENA2 (RENB2) control input
can be grounded (see Figure 14). In this configuration, the Write Enable 2/
Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin
operates as a control to load and read the programmable flag offsets.
Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/
72821/72831/72841/72851 configured for an 18-bit width-expansion
WIDTH EXPANSION CONFIGURATION — Word width may be in-
creased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the endpoint
status flags EFA and EFB, also FFA and FFB). The partial status flags
PAEA, PAFB, PAEA and PAFB can be detected from any one device.
Figure 15 demonstrates an 18-bit word width using the two FIFOs contained
in one IDT72801/72811/72821/72831/72841/72851. Any word width can
be attained by adding additional IDT72801/72811/72821/72831/72841/
72851s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (RENA2 and RENB2) control inputs can be grounded (see
Figure 15). In this configuration, the Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) pins are set LOW at Reset so that the pin operates as a
controltoloadandreadtheprogrammableflagoffsets.
Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs
configured as a single device
QA0 - QA8 (QB0 - QB8)
DA0 - DA8 (DB0 - DB8)
RSA (RSB)
RCLKA (RCLKB)
RENA1 (RENB1)
OEA (OEB)
EFA (EFB)
PAEA (PAEB)
RENA2 (RENB2)
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2/
LDA (WENB2/LDB)
FFA (FFB)
PAFA (PAFB)
IDT
72801
72811
72821
72831
72841
72851
FIFO
A (B)
3034 drw 15
DATA IN
WRITE CLOCK
18
9
RSB
READ CLOCK
9
18
RENB2
RENA2
WRITE ENABLE
FFA
EFB
OUTPUT ENABLE
READ ENABLE
9
WRITE ENABLE/LOAD
FFB
EFA
RSA
RAM
ARRAY
B
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
RAM
ARRAY
A
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
DATA OUT
RCLKA
EMPTY FLAG
RENB1
RENA1
OEB
OEA1
RCLKB
WCLKA
WCLKB
WENA1
WENB1
DA0 - DA8
DB0 - DB8
QA0 - QA8
QB0 - QB8
WENA2/
LDA
2WENB2/
LDB
RESET
9
FULL FLAG
3034 drw 16
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