參數(shù)資料
型號: IDT72831L15TF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: DUAL CMOS SyncFIFO
中文描述: 2K X 9 BI-DIRECTIONAL FIFO, 10 ns, PQFP64
封裝: SLIM, TQFP-64
文件頁數(shù): 8/16頁
文件大小: 169K
代理商: IDT72831L15TF
8
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72811
FFA
PAFA
PAEA
EFA
FFB
PAFB
PAEB
EFB
72801
0
1 to n
(1)
72821
0
1 to n
(1)
0
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
L
H
H
H
H
1 to n
(1)
(n+1) to (256-(m+1))
(256-m
(2)
to 255
256
(n+1) to (512-(m+1))
(512-m
(2)
to 511
512
(n+1) to (1,024-(m+1))
(1,024-m
(2)
to 1,023
1,024
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72841
0
1 to n
(1)
(n+1) to (4,096-(m+1))
(4,096-m
(2)
to 4,095
4,096
FFA
PAFA
PAEA
EFA
FFB
PAFB
PAEB
EFB
72831
0
1 to n
(1)
72851
0
1 to n
(1)
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
L
H
H
H
H
(n+1) to (2,048-(m+1))
(2,048-m
(2)
to 2,047
2,048
(n+1) to (8,192-(m+1))
(8,192-m
(2)
to 8,191
8,192
Programmable Almost–Full Flag
(
PAFA
,
PAFB
)
PAFA
(
PAFB
) will go
LOW when the amount of data in Array A (B) reaches the almost-full condition.
If no reads are performed after Reset,
PAFA
(
PAFB
) will go LOW after (256-m
writes to the IDT72801's FIFO A (B); (512-m writes to the IDT72811's FIFO
A (B); (1,024-m writes to the IDT72821's FIFO A (B); (2,048-m writes to the
IDT72831's FIFO A (B); (4,096-m writes to the IDT72841's FIFO A (B); or
(8,192-m writes to the IDT72851's FIFO A (B).
FFA
(
FFB
) is synchronized with respect to the LOW-to-HIGH transition of the
Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
registers.
If there is no Full offset specified,
PAFA
(
PAFB
) will go LOW at Full-7 words.
PAFA
(
PAFB
) is synchronized with respect to the LOW-to-HIGH transition
of WCLKA (WCLKB).
Programmable Almost–Empty Flag
(
PAEA
,
PAEB
)
PAEA
(
PAEB
) will
go LOW when the read pointer is "n+1" locations less than the write pointer. The
offset "n" is defined in the Empty Offset registers. If no reads are performed after
Reset,
PAEA
(
PAEB
) will go HIGH after "n+1" writes to FIFO A (B).
If there is no Empty offset specified,
PAEA
(
PAEB
) will go LOW at Empty+7
words.
PAEA
(
PAEB
) is synchronized with respect to the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
Data Outputs (QA
0
QA
8,
QB
0
QB
8
)
— QA
0
- QA
8
are the nine data
outputs for memory array A, QB
0
- QB
8
are the nine data outputs for memory
array B
.
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m= Full Offset (m= 7 default value)
相關(guān)PDF資料
PDF描述
IDT72831L15TFI DUAL CMOS SyncFIFO
IDT72831L25TF DUAL CMOS SyncFIFO
IDT72831L25TFI DUAL CMOS SyncFIFO
IDT72841L10PF DUAL CMOS SyncFIFO
IDT72841L10PFI DUAL CMOS SyncFIFO
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