IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9" />
參數(shù)資料
型號(hào): IDT72841L10TF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 3/16頁(yè)
文件大小: 0K
描述: IC FIFO SYNC 4KX9 10NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 7200
功能: 異步,雙端口
存儲(chǔ)容量: 36K(4K x 9)
訪問(wèn)時(shí)間: 10ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72841L10TF8
11
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLKA
(WCLKB)
DA0 - DA8
(DB0 - DB8)
FFA (FFB)
WENA1
(
WENB1)
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
RENA1
(
RENB2)
QA0 - QA8
(QB0 - QB8)
OEA
(
OEB)
3034 drw 09
tSKEW1
tDS
tSKEW1
tENH
NEXT DATA READ
DATA READ
tWFF
tENS
DATA IN OUTPUT REGISTER
LOW
NO WRITE
tA
tENS
(1)
tENS
(1)
tENH
NO WRITE
tDH
tDS
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tENH
DATA WRITE 2
WCLKA (WCLKB)
DA0 - DA8
(DB0 - DB8)
RCLKA (RLCKB)
EFA (EFB)
RENA1, RENA2
(
RENB1, RENB2)
DATA READ
tSKEW1
tFRL
(1)
tSKEW1
WENA2 (WENB2)
(If Applicable)
tREF
WENA1, (WENB1)
3034 drw 10
DATA WRITE 1
tREF
(1)
LOW
OEA (OEB)
QA0-QA8
(QB0-QB8)
DATA IN OUTPUT REGISTER
tA
NOTE:
1. When tSKEW1
≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1
< minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
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