IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9," />
參數(shù)資料
型號(hào): IDT72841L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 4KX9 15NS 64QFP
標(biāo)準(zhǔn)包裝: 90
系列: 7200
功能: 異步,雙端口
存儲(chǔ)容量: 36K(4K x 9)
訪問(wèn)時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤
其它名稱: 72841L15PF
7
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
LDA
LDA WENA1
WENA1
WCLKA
OPERATION ON FIFO A
LDB
LDB WENB1
WENB1
WCLKB
OPERATION ON FIFO B
00
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
NoOperation
1
0
Write Into FIFO
1
NoOperation
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
Figure 2. Writing to Offset Registers for FIFOs A and B
A read and write should not be performed simultaneously to the offset
registers.
OUTPUTS:
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations,when ArrayA(B)isfull. Ifnoreadsareperformedafterreset,FFA
(FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes
totheIDT72811'sFIFOA(B);1,024writestotheIDT72821'sFIFOA(B);2,048
writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A
(B); or 8,192 writes to the IDT72851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe
WriteClockWCLKA(WCLKB).
EmptyFlag(EFA, EFB)—EFA(EFB)willgoLOW,inhibitingfurtherread
operations,whenthereadpointerisequaltothewritepointer,indicatingthat
Array A (B) is empty.
EFA(EFB)is synchronizedwithrespecttotheLOW-to-HIGHtransitionof
the Read Clock RCLKA (RCLKB).
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72801 - DUAL 256 x 9
72811 - DUAL 512 x 9
7
80
(MSB)
1
00
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72831 - DUAL 2,048 x 9
72851 - DUAL 8,192 x 9
7
80
(MSB)
0
2
(MSB)
0
3
80
(MSB)
0
2
(MSB)
0
3
80
8
0
80
(MSB)
1
0
3034 drw 04
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72841 - DUAL 4,096 x 9
7
80
(MSB)
0
4
80
(MSB)
0
4
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
72821 - DUAL 1,024 x 9
7
80
(MSB)
0
1
80
(MSB)
0
1
NOTE:
1. For the purposes of this table, WENA2 and WENB2 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and
RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-
HIGH transition of RCLKA (RCLKB).
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參數(shù)描述
IDT72841L-15PF 制造商:Integrated Device Technology Inc 功能描述:FIFO, 2 x 4K x 9, Synchronous, 64 Pin, Plastic, QFP
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