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參數(shù)資料
| 型號： | IDT728981J8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 256X256 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 450 |
| 系列： | 7200 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 4:4 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 728981J8 |
4
Commercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
SO.TWARE CONTROL
If the A5 address line input is LOW then the IDT728981 Internal Control
Register is addressed. If A5 input line is high, then the remaining address input
linesareusedtoselectthe32possiblechannelsperinputoroutputstream. The
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT728981 Data and
Connectionmemories.TheIDT728981memorymappingisillustratedinTable
2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
Stream Address bits, Split Memory and Processor Mode bits. In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory as specified by the Memory Select Bits (Bits 4
and 3 of the Control Register). The Memory Select bits allow the Connection
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream
Address bits define internal memory subsections corresponding to input or
outputstreams.
The Processor Enable bit (bit 6) places EVERY output channel on every
output stream in Processor mode; i.e., the contents of the Connection Memory
LOW(CML,seeTable5))areoutputontheTXoutputstreamsonceeveryframe
unlesstheODEinputpinisLOW.IfPEbitisHIGH,thentheIDT728981behaves
as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection
MemoryHigh(CMH)locationsweresettoHIGH,regardlessoftheactualvalue.
Connection Memory High
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
100001
100010
111111
Data Memory
0
1
0
2
1
3
0
1
0
1
100000
Channel 2
Channel 31
Connection Memory Low
Stream
Control Register
CRb7
External Address Bits
A5-A0
5703 drw07
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CRb6CRb5CRb4CRb3CRb2CRb1CRb0
CRb1CRb0
CRb4CRb3
Figure 3.
Address Mapping
IfPEisLOW,thenbit2and0ofeachConnectionMemoryHighlocationoperates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
or disables (if LOW) the output stream and channel.
INITIALIZATION OF THE IDT728981
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
into the high impedance state. Care should be taken that no two connected TX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
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