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參數(shù)資料
| 型號： | IDT7290820PQFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 2048X2048 100-PQFP |
| 標準包裝： | 33 |
| 系列： | 7200 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 16:16 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 7290820PQFG |
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12
COMMERCIALTEMPERATURERANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 8 INTER.ACE MODE SELECTION (IMS) REGISTER BITS
TABLE 9 SERIAL DATA RATE SELECTION (16 INPUT x 16 OUTPUT)
DR1
DR0
Data Rate Selected
Master Clock Required
0
2.048 Mb/s
4.096 MHz
0
1
4.096 Mb/s
8.192 MHz
1
0
8.192 Mb/s
16.384 MHz
1
Reserved
Read/Write Address:
01H,
Reset Value:
0000H.
Bit
Name
Description
15-10
Unused
Must be zero for normal operation.
9-5
BPD4-0
These bits carry the value to be loaded into the connection memory block whenever the memory block
(Block Programming Data)
programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.
4
BPE
A zero to one transition of this bit enables the memory block programming function. The BPE and
(Begin Block Programming
BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set
Enable)
HIGH, the device requires two frames to complete the block programming. After the programming function
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
3
OSB
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When
(Output Stand By)
ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15
output drivers function normally.
2
SFE
A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
(Start Frame Evaluation)
register changes from zero to one, the evaluation procedure stops. To start another fame evaluation
cycle, set this bit to zero for at least one frame.
1-0
DR0-1
Input/Output data rate selection. See Table 9 for detailed programming.
(Data Rate Select)
15
14
13
12
11
10
9876543210
000000
BPD4 BPD3 BPD2 BPD1 BPD0
BPE
OSB
SFE
DR1
DR0
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