- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377427 > IDT72T18105L6-7BBI (Integrated Device Technology, Inc.) 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS PDF資料下載
參數(shù)資料
| 型號： | IDT72T18105L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 54/55頁 |
| 文件大?。?/td> | 540K |
| 代理商： | IDT72T18105L6-7BBI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁
54
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T1845 can easily be adapted to applications requiring depths
greater than 2,048 when the x18 Input or x18 Output bus Width is selected, 4,096
for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the
IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the
IDT72T18125. When both x9 Input and x9 Output bus Widths are selected,
depths greater than 4,096 can be adapted for the IDT72T1845, 8,192 for the
IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875,
65,536 for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the
IDT72T8105, 524,288 for the IDT72T18115 and 1,048,576 for the
IDT72T18125. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total depth equivalent
to the sumof the depths associated with each single FIFO. Figure 37 shows
a depth expansion using two IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass fromone FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's
OR
line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
OR
of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sumof the delays
for each individual FIFO:
(N – 1)*4*transfer clock) + 3*T
RCLK
where N is the number of FIFOs in the expansion and T
RCLK
is the RCLK period.
Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the
OR
flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading froma full depth expansion
configuration will "bubble up" fromthe last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's
IR
line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for
IR
of the first
FIFO in the chain to go LOW after a word has been read fromthe last FIFO is
the sumof the delays for each individual FIFO:
(N – 1)*3*transfer clock) + 2 T
WCLK
where N is the number of FIFOs in the expansion and T
WCLK
is the WCLK
period. Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the
IR
flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
Figure 37. Block Diagram of Depth Expansion
For the x18 Input or x18 Output bus Width:
4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18, 524,288 x 18 and 1,048,576 x 18
For both x9 Input and x9 Output bus Widths:
8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9, 262,144 x 9, 524,288 x 9, 1,048,576 x 9 and 2,097,152 x 9
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
n
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5909 drw41
n
n
FWFT/SI
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
FWFT/SI
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
FWFT/SI
RCS
READ CHIP SELECT
RCS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T18115L6-7BBI | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| IDT72T18125L6-7BBI | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| IDT72T20108 | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L4BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L5BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T18115L10BB | 功能描述:IC FIFO 262KX18 2.5V 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18115L4-4BB | 功能描述:IC FIFO 262KX18 2.5V 4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18115L5BB | 功能描述:IC FIFO 262KX18 2.5V 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18115L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 262KX18 2.5V 5NS 240BGA |
| IDT72T18115L5BBI | 功能描述:IC FIFO 262KX18 2.5V 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。