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參數(shù)資料
| 型號： | IDT72T18125L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進(jìn)先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 24/55頁 |
| 文件大?。?/td> | 540K |
| 代理商： | IDT72T18125L6-7BBI |
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24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
The MARK input must remain HIGH during the whole period of retransmt
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmt mode and into normal mode. Any number of MARK locations can be
set during FIFO operation, only the last marked location taking effect. Once a
mark location has been set the write pointer cannot be incremented past this
marked location. During retransmt mode write operations to the device may
continue without hindrance.
FIRST WORD FALL THROUGH/SERIAL IN
(
)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determnes whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag
(
EF
) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (
FF
) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read fromthe FIFO, including
the first, must be requested using the Read Enable (
REN
) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR
) to indicate whether or not there
is valid data at the data outputs (Q
n)
. It also uses Input Ready (
IR
) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Q
n
after three RCLK
rising edges,
REN
= LOW is not necessary. Subsequent words must be
accessed using the Read Enable (
REN
) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading
PAE
and
PAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programmng using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
If Synchronous operation of the write port has been selected via
ASYW
, this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permssible to stop the WCLK. Note that while WCLK is idle, the
FF
/
IR
,
PAF
and
HF
flags will not be updated. (Note that WCLK is only capable of
updating
HF
flag to LOW). The Write and Read Clocks can either be
independent or coincident.
If Asynchronous operation has been selected this input is WR (write strobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE (
WEN
)
When the
WEN
input is LOW, data may be loaded into the FIFO RAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAMarray sequentially and independently of any ongoing read
operation.
When
WEN
is HIGH, no new data is written in the RAMarray on each WCLK
cycle.
To prevent data overflow in the IDT Standard mode,
FF
will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF
will go HIGH allowing a write to occur. The
FF
is updated by two WCLK
cycles + t
SKEW
after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR
will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IR
will go
LOW allowing a write to occur. The
IR
flag is updated by two WCLK cycles +
t
SKEW
after the valid RCLK cycle.
WEN
is ignored when the FIFO is full in either FWFT or IDT Standard mode.
If Asynchronous operation of the write port has been selected, then WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
If Synchronous operation of the read port has been selected via
ASYR
, this
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permssible to stop the RCLK. Note that while RCLK is idle, the
EF
/
OR
,
PAE
and
HF
flags will not be updated. (Note that RCLK is only capable of updating
the
HF
flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read fromthe FIFO via the output register
whenever there is a rising edge on RD. In this mode the
REN
and
RCS
inputs
must be tied LOW. The
OE
input is used to provide Asynchronous control of the
three-state Qn outputs.
WRITE CHIP SELECT (
WCS
)
The
WCS
disables all Write Port inputs (data only) if it is held HIGH. To
performnormal operations on the write port, the
WCS
must be enabled, held
LOW.
READ ENABLE (
REN
)
When Read Enable is LOW, data is loaded fromthe RAMarray into the
output register on the rising edge of every RCLK cycle if the device is not empty.
When the
REN
input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q
0
-Q
n
maintain the previous data value.
In the IDT Standard mode, every word accessed at Q
n
, including the first
word written to an empty FIFO, must be requested using
REN
provided that
RCS
is LOW. When the last word has been read fromthe FIFO, the Empty Flag
(
EF
) will go LOW, inhibiting further read operations.
REN
is ignored when the
FIFO is empty. Once a write is performed,
EF
will go HIGH allowing a read to
occur. The
EF
flag is updated by two RCLK cycles + t
SKEW
after the valid WCLK
cycle. Both
RCS
and
REN
must be active, LOW for data to be read out on the
rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Q
n
, on the third valid LOW-to-HIGH transition of RCLK + t
SKEW
after the first write.
REN
and
RCS
do not need to be asserted LOW for the First
Word to fall through to the output register. In order to access all other words,
a read must be executed using
REN
and
RCS
. The RCLK LOW-to-HIGH
transition after the last word has been read fromthe FIFO, Output Ready (
OR
)
will go HIGH with a true read (RCLK with
REN
= LOW;
RCS
= LOW), inhibiting
further read operations.
REN
is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then
REN
must be held active, (tied LOW).
SERIAL ENABLE (
SEN
)
The
SEN
input is an enable used only for serial programmng of the offset
registers. The serial programmng method must be selected during Master
Reset.
SEN
is always used in conjunction with
LD
. When these lines are both
LOW, data at the SI input can be loaded into the programregister one bit for each
LOW-to-HIGH transition of SCLK.
When
SEN
is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN
functions the same way in both IDT
Standard and FWFT modes.
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