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參數(shù)資料
| 型號： | IDT72T20108L4BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 64K X 20 OTHER FIFO, 3.2 ns, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 19/51頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IDT72T20108L4BB |
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19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
OUTPUT ENABLE (
OE
)
When Output Enable is LOW, the parallel output buffers receive data from
the output register. When
OE
is HIGH, the output data bus (Qn) goes into a
high-impedance state. During Master or Partial Reset the
OE
is the only input
that can place the output data bus into high-impedance. During reset the
RCS
input can be HIGH or LOW and has no effect on the output data bus.
READ CHIP SELECT (
RCS
)
The Read Chip Select input provides synchronous control of the Read
output port. When
RCS
goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the low-impedance state. When
RCS
goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to high-impedance. During
a Master or Partial Reset the
RCS
input has no effect on the Qn output bus,
OE
is the only input that provides high-impedance control of the Qn outputs. If
OE
is LOW, the Qn data outputs will be low-impedance regardless of
RCS
until the
first rising edge of RCLK after a reset is complete. Then if
RCS
is HIGH the
data outputs will go to high-impedance.
The
RCS
input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, the
EF
will still go fromLOW to HIGH
based on a rising edge of RCLK, regardless of the state of the
RCS
input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS
. For this reason the user should pay extra
attention when a data word is written to an empty FIFO in FWFT mode. If
RCS
is HIGH when an empty FIFO is written into, the first word will fall through to the
output register but will not be available on the Qn outputs because they are in
high-impedance. The user must take
RCS
active LOW to access this first word,
placing the output bus in low-impedance.
REN
must remain HIGH for at least
one cycle after
RCS
has gone LOW. A rising edge of RCLK with
RCS
and
REN
LOW will read out the next word. Care must be taken so as not to lose the
first word written to an empty FIFO when
RCS
is HIGH. Refer to Figure 22,
RCS
and
REN
Read Operation (FWFT Mode).
The
RCS
pin must also be
active (LOW) in order to performa Retransmt. See Figure 18 for
Read Cycle
and Read Chip Select Timng (IDT Standard Mode).
See Figure 21 for
Read
Cycle and Read Chip Select Timng (FWFT Mode).
WRITE CHIP SELECT (
WCS
)
The
WCS
disables all Write Port inputs (data only) if it is held HIGH. To
performnormal operations on the write port, the
WCS
must be enabled.
HSTL SELECT (HSTL)
The inputs that were listed in Table 6 can be setup to be either HSTL or
LVTTL. If HSTL is HIGH, then HSTL operation of those signals will be se-
lected. If HSTL is LOW , then LVTTL will be selected.
BUS-MATCHING (IW, OW)
The pins IW, and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Table 7 for Bus-
Matching Write to Read Ratio.
FLAG SELECT BITS (FSEL0 and FSEL1)
These pins will select the four default offset values for the
PAE
and
PAF
flags
during Master Reset. The four possible settings are listed on Table 3. Note that
the status of these inputs should not change after Master Reset.
OUTPUTS:
DATA OUT (Q0-Q19)
(Q0 – Q19) are data outputs for 20-bit wide data, or (Q0 – Q9) are data
outputs for 10-bit wide data.
FULL FLAG (
FF
/
IR
)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF
) function
is selected. When the FIFO is full,
FF
will go LOW, inhibiting further write
operations. When
FF
is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS
or
PRS
),
FF
will go LOW after D writes to the FIFO.
If x20 Input or x20 Output bus width is selected, D = 32,768 for the IDT72T2098,
65,536 for the IDT72T20108, 131,072 for the IDT72T20118 and 262,144 for
the IDT72T20128. If both x10 Input and x10 Output bus widths are selected,
D = 65,536 for the IDT72T2098, 131,072 for the IDT72T20108, 262,144 for
the IDT72T20118 and 524,288 for the IDT72T20128. See Figure 10,
Write
Cycle and Full Flag Timng (IDT Standard Mode)
, for the relevant timng
information.
In FWFT mode, the Input Ready (
IR
) function is selected.
IR
goes LOW
when memory space is available for writing in data. When there is no longer
any free space left,
IR
goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either
MRS
or
PRS
),
IR
will go HIGH after D writes
to the FIFO. If x20 Input or x20 Output bus Width is selected, D = 32,769 for the
IDT72T2098, 65,537 for the IDT72T20108, 131,073 for the IDT72T20118 and
262,145 for the IDT72T20128. If both x10 Input and x10 Output bus Widths are
selected, D = 65,537 for the IDT72T2098, 131,073 for the IDT72T20108,
262,145 for the IDT72T20118 and 524,289 for the IDT72T20128. See Figure
19,
Write Timng (FWFT Mode)
, for the relevant timng information.
The
IR
status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IR
is one greater than needed to
assert
FF
in IDT Standard mode.
FF
/
IR
is synchronous and updated on the rising edge of WCLK.
FF
/
IR
are
double register-buffered outputs.
Note, when the device is in Retransmt mode, this flag is a comparison of the
write pointer to the “marked” location. This differs fromnormal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF
/
OR
)
This is a dual-purpose pin. In the IDT Standard mode, the Empty Flag (
EF
)
function is selected. When the FIFO is empty,
EF
will go LOW, inhibiting further
read operations. When
EF
is HIGH, the FIFO is not empty. See Figure 12,
Read
Cycle, Empty Flag and First Word Latency Timng (IDT Standard Mode
), for
the relevant timng information.
In FWFT mode, the Output Ready (
OR
) function is selected.
OR
goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
OR
stays LOW after the RCLK LOW to HIGH transition that shifts the
last word fromthe FIFO memory to the outputs.
OR
goes HIGH only with a true
read (RCLK with
REN
= LOW). The previous data stays at the outputs, indicating
the last word was read. Further data reads are inhibited until
OR
goes LOW
again. See Figure 20,
Read Timng (FWFT Mode
), for the relevant timng
information.
EF
/
OR
is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF
is a double register-buffered output. In FWFT
mode,
OR
is a triple register-buffered output.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20108L5BB | 功能描述:IC FIFO 327768X20 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20108L6-7BB | 功能描述:IC FIFO 327768X20 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L10BB | 功能描述:IC FIFO 65536X20 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L4BB | 功能描述:IC FIFO 65536X20 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L5BB | 功能描述:IC FIFO 65536X20 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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