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| 型號： | IDT72T20108L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 64K X 20 OTHER FIFO, 3.6 ns, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大小： | 496K |
| 代理商： | IDT72T20108L5BB |
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20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
)
The Programmable Almost-Full flag (
PAF
) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS
),
PAF
will go LOW after (D - m words are written
to the FIFO. If x20 Input or x20 Output bus width is selected,
PAF
will go LOW
after (32,768-m writes for the IDT72T2098, (65,536-m writes for the
IDT72T20108, (131,072-m writes for the IDT72T20118 and (262,144-m
writes for the IDT72T20128. If both x10 Input and x10 Output bus widths are
selected,
PAF
will go LOW after (65,536-m writes for the IDT72T2098,
(131,072-m writes for the IDT72T20108, (262,144-m writes for the
IDT72T20118 and (524,288-m writes for the IDT72T20128, respectively.
The offset “m” is the full offset value. The default setting for this value is listed in
Table 3.
In FWFT mode, if x20 Input or x20 Output bus width is selected,
PAF
will go
LOW after (32,769-m writes for the IDT72T2098, (65,537-m writes for the
IDT72T20108, (131,073-m writes for the IDT72T20118 and (262,145-m
writes for the IDT72T20128. If both x10 Input and x10 Output bus widths are
selected,
PAF
will go LOW after (65,537-m writes for the IDT72T2098,
(131,073-m writes for the IDT72T20108, (262,145-m writes for the
IDT72T20118 and (524,289-m writes for the IDT72T20128, respectively.
The offset mis the full offset value. The default setting for this value is listed in
Table 3.
See Figure 29,
Programmable Almost-Full Flag Timng (IDT Standard and
FWFT Mode
), for the relevant timng information.
Note, when the device is in Retransmt mode, this flag is a comparison of the
write pointer to the “marked” location. This differs fromnormal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
)
The Programmable Almost-Empty flag (
PAE
) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode,
PAE
will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 3.
In FWFT mode, the
PAE
will go LOW when there are n+1 words or less in
the FIFO. The default setting for this value is stated in Table 3.
See Figure 30,
Programmable Almost-Empty Flag Timng (IDT Standard
and FWFT Mode
), for the relevant timng information.
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via HSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of
REN
and
RCS
.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data fromthe Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times.
These variations in access time maybe caused by ambient temperature, sup-
ply voltage, or device characteristics. The ERCLK output also compensates
for any trace length delays between the Qn data outputs and receiving de-
vices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the FIFO device, therefore the
ERCLK output level transitions should always be at the same position in time
relative to the data outputs. Note, that ERCLK is guaranteed by design to be
slower than the slowest Qn, data output. Refer to Figure 4,
Echo Read Clock
and Data Output Relationship
, Figure 27,
Echo Read Clock & Read Enable
Operation in Double Data Rate Mode
and Figure 28,
Echo RCLK & Echo
REN
Operation
for timng information.
ECHO READ ENABLE (
EREN
)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via HSTL.
The
EREN
output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for
reading data fromthe Qn output port at high speeds. The
EREN
output is
controlled by internal logic that behaves as follows: The
EREN
output is active
LOW for the RCLK cycle that a new word is read out of the FIFO. That is, a
rising edge of RCLK will cause
EREN
to go active, LOW if both
REN
and
RCS
are active, LOW and the FIFO is NOT empty.
Figure 4. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN
is LOW.
2. t
ERCLK
> t
A
, guaranteed by design.
3. Qslowest is the data output with the slowest access time, t
A
.
4. Time, t
D
is greater than zero, guaranteed by design.
5.
REN
=
RCS
=
OE
= 0.
5996 drw07
ERCLK
t
A
Q
SLOWEST
(3)
RCLK
t
ERCLK
t
ERCLK
t
A
t
D
t
D
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| IDT72T20108L5BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20108L6BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20108L6BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20108L7BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20108L7BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20108L6-7BB | 功能描述:IC FIFO 327768X20 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L10BB | 功能描述:IC FIFO 65536X20 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L4BB | 功能描述:IC FIFO 65536X20 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L5BB | 功能描述:IC FIFO 65536X20 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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