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參數(shù)資料
| 型號： | IDT72T20108L6BB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 2.5伏高速TeraSync⑩復員/特別提款權先進先出20-BIT/10-BIT配置 |
| 文件頁數(shù)： | 50/51頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IDT72T20108L6BB |
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50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
DEPTH EXPANSION CONFIGURATION IN SINGLE DATA RATE
(FWFT MODE ONLY)
The IDT72T2098 can easily be adapted to applications requiring depths
greater than 32,768 when the x20 Input or x20 Output bus width is selected,
65,536 for the IDT72T20108, 131,072 for the IDT72T20118 and 262,144 for
the IDT72T20128. When both x10 Input and x10 Output bus widths are
selected, depths greater than 65,536 can be adapted for the IDT72T2098,
131,072 for the IDT72T20108, 262,144 for the IDT72T20118 and 524,288 for
the IDT72T20128. In FWFT mode, the FIFOs can be connected in series (the
data outputs of one FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total depth equivalent
to the sumof the depths associated with each single FIFO. Figure 32 shows a
depth expansion using two IDT72T2098/72T20108/72T20118/72T20128
devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. Also, the devices must be operating in
Single Data Rate mode since that is the only mode available in FWFT. The first
word written to an empty configuration will pass fromone FIFO to the next ("ripple
down") until it finally appears at the outputs of the last FIFO in the chain – no read
operation is necessary but the RCLK of each FIFO must be free-running. Each
time the data word appears at the outputs of one FIFO, that device's
OR
line goes
LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
OR
of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sumof the delays
for each individual FIFO:
(N – 1)*4*transfer clock) + 3*T
RCLK
where N is the number of FIFOs in the expansion and T
RCLK
is the RCLK period.
Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the
OR
flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading froma full depth expansion
configuration will "bubble up" fromthe last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's
IR
line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for
IR
of the first
FIFO in the chain to go LOW after a word has been read fromthe last FIFO is
the sumof the delays for each individual FIFO:
(N – 1)*3*transfer clock) + 2 T
WCLK
where N is the number of FIFOs in the expansion and T
WCLK
is the WCLK
period. Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the
IR
flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
Figure 32. Block Diagram of Depth Expansion in Single Data Rate Mode
For the x20 Input or x20 Output bus Width: 65,536 x 20, 131,072 x 20, 262,144 x 20 and 524,288 x 20
For both x10 Input and x10 Output bus Widths: 131,072 x 10, 262,144 x 10, 524,288 x 10 and 1,048,576 x 10
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
n
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5996 drw35
n
n
FWFT
FWFT
FWFT
IDT
72T2098
72T20108
72T20118
72T20128
RCS
READ CHIP SELECT
RCS
IDT
72T2098
72T20108
72T20118
72T20128
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72T20108L6BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20108L7BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20108L7BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20118 | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20118L10BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20118L10BB | 功能描述:IC FIFO 65536X20 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L4BB | 功能描述:IC FIFO 65536X20 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L5BB | 功能描述:IC FIFO 65536X20 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L6-7BB | 功能描述:IC FIFO 65536X20 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L10BB | 功能描述:IC FIFO 1KX20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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