參數(shù)資料
型號(hào)： IDT72T20118L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述： 128K X 20 OTHER FIFO, 3.6 ns, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù)： 9/51頁
文件大?。?/td> 496K
代理商： IDT72T20118L5BB
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Symbol
V
TERM
Rating
Commercial
–0.5 to +3.6
(2)
Unit
V
Termnal Voltage
with respect to GND
T
STG
Storage Temperature
–55 to +125
°
C
–50 to +50 mA
I
OUT
DC Output Current
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 2.5V ± 0.125V, T
A
= 0
°
C to +70
°
C;Industrial: V
CC
= 2.5V ± 0.125V, T
A
= -40
°
C to +85
°
C)
Symbol
Parameter
I
LI
Input Leakage Current
Min.
–10
Max.
10
Unit
μ
A
μ
A
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
I
LO
V
OH
(5)
Output Leakage Current
Output Logic “1” Voltage,
–10
10
—
—
—
0.4V
0.4V
0.4V
20
60
60
10
50
50
I
OH
= –8 mA @V
DDQ
= 2.5V
±
0.125V (LVTTL)
I
OH
= –8 mA @V
DDQ
= 1.8V
±
0.1V (eHSTL)
I
OH
= –8 mA @V
DDQ
= 1.5V
±
0.1V (HSTL)
I
OL
= 8 mA @V
DDQ
= 2.5V
±
0.125V (LVTTL)
I
OL
= 8 mA @V
DDQ
= 1.8V
±
0.1V (eHSTL)
I
OL
= 8 mA @V
DDQ
= 1.5V
±
0.1V (HSTL)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
V
DDQ
-0.4
V
DDQ
-0.4
V
DDQ
-0.4
—
—
—
—
—
—
—
—
—
V
OL
Output Logic “0” Voltage,
I
CC1
(1,2)
Active V
CC
Current (V
CC
= 2.5V)
I
CC2
(1)
Standby V
CC
Current (V
CC
= 2.5V)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
V
CC
Supply Voltage
GND
Supply Voltage
V
IH
Input High Voltage
LVTTL
eHSTL
HSTL
V
IL
Input Low Voltage
LVTTL
eHSTL
HSTL
V
REF
Voltage Reference Input
eHSTL
(HSTL only)
HSTL
T
A
Operating Temperature Commercial
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. V
CC
termnal only.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
(2,3)
Input
V
IN
= 0V
10
(3)
pF
Capacitance
Output
Capacitance
C
OUT
(1,2)
V
OUT
= 0V
10
pF
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
NOTES:
1. With output deselected, (
OE
≥
V
IH
).
2. Characterized values, not currently tested.
3. C
IN
for Vref is 20pF.
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz.
WCS
= HIGH,
REN
or
RCS
= HIGH.
2. Typical I
CC1
calculation
:
for LVTTL I/O I
CC1
(mA) = 0.6mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O I
CC1
(mA) = 38mA + (0.7mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)
3. Typical I
DDQ
calculation: With Data Outputs in High-Impedance: I
DDQ
(mA) = 0.15mA x fs
With Data Outputs in Low-Impedance: I
DDQ
(mA) = (C
L
x V
DDQ
x fs x 2N)/2000
fs = WCLK frequency = RCLK frequency (in MHz), V
DDQ
= 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.
t
A
= 25°C, C
L
= capacitive load (pf)
4. Total Power consumed: PT = [(V
CC
x I
CC
) + (V
DDQ
x I
DDQ
)].
5. Outputs are not 3.3V tolerant.
Min.
2.375
0
1.7
V
REF
+0.2
V
REF
+0.2
-0.3
—
—
0.8
0.68
Typ.
2.5
0
—
—
—
—
—
—
0.9
0.75
Max.
2.625
0
3.45
—
—
0.7
V
REF
-0.2
V
REF
-0.2
1.0
0.9
Unit
V
V
V
V
V
V
V
V
V
V
°
C
°
C
0
—
70
T
A
Operating Temperature Industrial
-40
—
85
NOTE:
1. V
REF
is only required for HSTL or eHSTL inputs. V
REF
should be tied LOW for LVTTL operation.
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