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參數(shù)資料
| 型號： | IDT72T20118L6BB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 2.5伏高速TeraSync⑩復(fù)員/特別提款權(quán)先進先出20-BIT/10-BIT配置 |
| 文件頁數(shù)： | 7/51頁 |
| 文件大小： | 496K |
| 代理商： | IDT72T20118L6BB |
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7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PIN DESCRIPTION (CONTINUED)
Symbol &
Name
Pin No.
RCS
(F14)
Read Chip
Select
HSTL-LVTTL
RCS
provides synchronous enable/disable control of the read port and High-Impedance control of the
INPUT
Qn data outputs, synchronous to RCLK. When using
RCS
the
OE
pin must be tied LOW. During Master
or Partial Reset the
RCS
input is dont care, if
OE
is LOW the data outputs will be Low-Impedance regardless
of
RCS
.
HSTL-LVTTL When LOW and in DDR mode,
REN
along with a rising and falling edge of RCLK will send data in FIFO
INPUT
memory to the output register and read the current data in output register. In SDR mode data will only
be read on the rising edge of RCLK only.
Read Single
LVTTL
When LOW, this input pin sets the read port to Single Data Clock mode. When HIGH, the read port will
Data Rate
INPUT
operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during
operation.
Retransmt
HSTL-LVTTL
RT
asserted on the rising edge of RCLK initializes the read pointer to the first location in memory.
EF
flag
INPUT
is set to LOW (
OR
to HIGH in FWFT mode). The write pointer, offset registers, and flag settings are not
affected. If a mark has been set via the MARK input pin, then the read pointer will initialize to the mark location
when
RT
is asserted.
Serial Clock
LVTTL
A rising edge of SCLK will clock the serial data present on the SI input into the offset registers provided
INPUT
that
SEN
is enabled. A rising edge of SCLK will also read data out of the offset registers provided that
SREN
is enabled.
Serial Input
HSTL-LVTTL
SEN
used in conjunction with SI and SCLK enables serial loading of the programmable flag offsets.
Enable
INPUT
Serial Read
HSTL-LVTTL
SREN
used in conjunction with SO and SCLK enables serial reading of the programmable flag offsets.
Enable
INPUT
Serial Input
HSTL-LVTTL This input pin is used to load serial data into the programmable flag offsets. Used in conjunction with
SEN
INPUT
and SCLK.
Serial Output
HSTL-LVTTL This output pin is used to read data fromthe programmable flag offsets. Used in conjunction with
SREN
OUTPUT
and SCLK.
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four termnals required by IEEE Standard 1149.1-1990. Test
INPUT
operations of the device are synchronous to TCK. Data fromTMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
JTAG Test Data HSTL-LVTTL One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Input
INPUT
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
JTAG Test Data HSTL-LVTTL One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Output
OUTPUT
operation, test data serially loaded output via the TDO on the falling edge of TCK fromeither the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. One of four termnals required by IEEE Standard 1149.1-1990. TMS directs the
Select
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
JTAG Reset
HSTL-LVTTL
TRST
is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
INPUT
automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH
for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-
impedance. If the JTAG function is used but the user does not want to use
TRST
, then
TRST
can be tied
with
MRS
to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be
tied to GND. An internal pull-up resistor forces
TRST
HIGH if left unconnected.
Write Clock
HSTL-LVTTL Input clock when used in conjunction with
WEN
for writing data into the FIFO memory.
INPUT
Write Chip Select HSTL-LVTTL The
WCS
pin an be regarded as a second
WEN
input, enabling/disabling write operations.
INPUT
Write Enable
HSTL-LVTTL When LOW and in DDR mode,
WEN
along with a rising and falling edge of WCLK will write data into the
INPUT
FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.
REN
(F16)
Read Enable
RSDR
(1)
(L2)
RT
(F15)
SCLK
(H15)
SEN
(J15)
SREN
(J16)
SI
(H16)
SO
(K15)
TCK
(2)
(F1)
TDI
(2)
(E2)
TDO
(2)
(F3)
TMS
(2)
(F2)
TRST
(2)
(E3)
WCLK
(G1)
WCS
(H2)
WEN
(H1)
I/O TYPE
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20128L10BB | 功能描述:IC FIFO 1KX20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L4BB | 功能描述:IC FIFO 1KX20 2.5V 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L4BBG | 功能描述:IC FIFO 1KX20 2.5V 4NS 208BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L5BB | 功能描述:IC FIFO 1KX20 2.5V 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L6-7BB | 功能描述:IC FIFO 1KX20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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