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參數(shù)資料
| 型號： | IDT72T20128L4BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 256K X 20 OTHER FIFO, 3.2 ns, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 13/51頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IDT72T20128L4BB |
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13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T2098/72T20108/72T20118/72T20128 support two different
timng modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determned during
Master Reset, by the state of the FWFT input.
If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag
(
EF
) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (
FF
)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read fromthe FIFO, including the first, must be
requested using the Read Enable (
REN
) and RCLK.
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR
) to indicate whether or not there
is valid data at the data outputs (Q
n)
. It also uses Input Ready (
IR
) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q
n
after three RCLK rising
edges,
REN
= LOW is not necessary. Subsequent words must be accessed
using the Read Enable (
REN
) and RCLK.
Various signals, both input and output signals operate differently depending
on which timng mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF
,
PAF
,
PAE
, and
EF
operate in the manner
outlined in Table 4. To write data into to the FIFO, Write Enable (
WEN
) must
be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (
EF
) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (
PAE
) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are listed in Table 2. This parameter
is also user programmable. See section on Programmable Flag Offset Loading.
Continuing to write data into the FIFO will cause the Programmable Almost-
Full flag (
PAF
) to go LOW. Again, if no reads are performed, the
PAF
will go
LOW after (D-m writes to the FIFO. If x20 Input or x20 Output bus Width is
selected, (D-m = (32,768-m writes for the IDT72T2098, (65,536-m writes
for the IDT72T20108, (131,072-m) writes for the IDT72T20118 and
(262,144-m writes for the IDT72T20128. If both x10 Input and x10 Output bus
Widths are selected, (D-m = (65,536-m writes for the IDT72T2098, (131,072-m
writes for the IDT72T20108, (262,144-m writes for the IDT72T20118 and
(524,288-m writes for the IDT72T20128. The offset “m” is the full offset value.
The default setting for these values are listed in Table 3. This parameter is also
user programmable. See the section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (
FF
) will go LOW, inhibiting further write
operations. If no reads are performed after a reset,
FF
will go LOW after D writes
to the FIFO. If the x20 Input or x20 Output bus Width is selected, D = 32,768
writes for the IDT72T2098, 65,536 writes for the IDT72T20108, 131,072 writes
for the IDT72T20118 and 262,144 writes for the IDT72T20128. If both x10
Input and x10 Output bus Widths are selected, D = 65,536 writes for the
IDT72T2098, 131,072 writes for the IDT72T20108, 262,144 writes for the
IDT72T20118 and 524,288 writes for the IDT72T20128, respectively.
If the FIFO is full, the first read operation will cause
FF
to go HIGH.
Subsequent read operations will cause
PAF
to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE
will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read fromthe FIFO, the
EF
will go LOW inhibiting
further read operations.
REN
is ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EF
and
FF
outputs are double
register-buffered outputs. IDT Standard mode is available when the device is
configured in both Single Data Rate mode and Double Data Rate mode.
Relevant timng diagrams for IDT Standard mode can be found in Figure
10, 11, 12, 13, 14, 15, 16, 17, 18 and 23.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR
,
PAF
,
PAE
, and
OR
operate in the manner
outlined in Table 5. To write data into the FIFO,
WEN
must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (
OR
)
flag will go LOW. Subsequent writes will continue to fill up the FIFO.
PAE
will go
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
Again, if no reads are performed, the
PAF
will go LOW after (D-m writes
to the FIFO. If x20 Input or x20 Output bus Width is selected, (D-m = (32,769-m
writes for the IDT72T2098, (65,537-m writes for the IDT72T20108, (131,073-m
writes for the IDT72T20118 and (262,145-m writes for the IDT72T20128. If
both x10 Input and x10 Output bus Widths are selected, (D-m = (65,537-m
writes for the IDT72T2098, (131,073-m writes for the IDT72T20108,
(262,145-m writes for the IDT72T20118 and (524,289-m writes for the
IDT72T20128. The offset mis the full offset value. The default setting for these
values are stated in the footnote of Table 3.
When the FIFO is full, the Input Ready (
IR
) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset,
IR
will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 32,769
writes for the IDT72T2098, 65,537 writes for the IDT72T20108, 131,073 writes
for the IDT72T20118 and 262,145 writes for the IDT72T20128. If both x10 Input
and x10 Output bus Widths are selected, D = 65,537 writes for the IDT72T2098,
131,073 writes for the IDT72T20108, 262,145 writes for the IDT72T20118 and
524,289 writes for the IDT72T20128, respectively. Note that the additional word
in FWFT mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR
flag to go LOW.
Subsequent read operations will cause the
PAF
to go HIGH at the conditions
described in Table 5. If further read operations occur, without write operations,
the
PAE
will go LOW when there are n+1 words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read fromthe FIFO,
OR
will go HIGH inhibiting
further read operations.
REN
is ignored when the FIFO is empty.
When configured in FWFT mode, the
OR
flag output is triple register-
buffered, and the
IR
flag output is double register-buffered. FWFT mode is only
available when the device is configured in Single Data Rate mode.
Relevant timng diagrams for FWFT mode can be found in Figure 19, 20,
21, 22, and 24.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T20128L4BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20128L5BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20128L5BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20128L6BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20128L6BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20128L4BBG | 功能描述:IC FIFO 1KX20 2.5V 4NS 208BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L5BB | 功能描述:IC FIFO 1KX20 2.5V 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L6-7BB | 功能描述:IC FIFO 1KX20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L10BB | 功能描述:IC FIFO 262X20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L4BB | 功能描述:IC FIFO 262X20 2.5V 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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