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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377427 > IDT72T20128L5BB (INTEGRATED DEVICE TECHNOLOGY INC) 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION PDF資料下載

參數(shù)資料

型號(hào)：	IDT72T20128L5BB
廠商：	INTEGRATED DEVICE TECHNOLOGY INC
元件分類：	DRAM
英文描述：	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述：	256K X 20 OTHER FIFO, 3.6 ns, PBGA208
封裝：	17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù)：	15/51頁
文件大小：	496K
代理商：	IDT72T20128L5BB

15

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS

32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10

Figure 3. Programmable Flag Offset Programming Sequence

Write Memory (DDR)

Write Memory (SDR)

Read Memory (DDR)

No Operation

5996 drw06

X

1

1

X

X

X

0

1

X

0

1

X

X

X

0

1

X

1

1

X

X

X

1

0

X

1

0

X

X

X

1

0

X

X

X

X

1

1

X

X

X

Read Memory (SDR)

IDT72T2098

IDT72T20108

IDT72T20118

IDT72T20128

x10 to x10 Mode

All Other Modes

WCLK

RCLK

X

WSDR

X

X

RSDR

X

X

SEN

0

1

X

SREN

1

0

SCLK

X

X

WEN

1

1

REN

1

1

x10 to x10 Mode

All Other Modes

Serial Write to registers:

In SDR Mode:

32 bits for the IDT72T2098

34 bits for the IDT72T20108

36 bits for the IDT72T20118

38 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Write to registers:

In SDR Mode:

30 bits for the IDT72T2098

32 bits for the IDT72T20108

34 bits for the IDT72T20118

36 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Read From registers:

In SDR Mode:

32 bits for the IDT72T2098

34 bits for the IDT72T20108

36 bits for the IDT72T20118

38 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Read from registers:

In SDR Mode:

30 bits for the IDT72T2098

32 bits for the IDT72T20108

34 bits for the IDT72T20118

36 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Write to registers:

In DDR Mode:

30 bits for the IDT72T2098

32 bits for the IDT72T20108

34 bits for the IDT72T20118

36 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Write to registers:

In DDR Mode:

28 bits for the IDT72T2098

30 bits for the IDT72T20108

32 bits for the IDT72T20118

34 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Read from registers:

In DDR Mode:

30 bits for the IDT72T2098

32 bits for the IDT72T20108

34 bits for the IDT72T20118

36 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

Serial Read from registers:

In DDR Mode:

28 bits for the IDT72T2098

30 bits for the IDT72T20108

32 bits for the IDT72T20118

34 bits for the IDT72T20128

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

NOTES:

1. The programmng sequence applies to both IDT Standard and FWFT modes.

2. When the input or output ports are in DDR mode, the depth is reduced by half but the overall density remains the same. For example, the IDT72T2098 in SDR mode is

32,768 x 20/65,536 x 10 = 655,360, in DDR mode the configuration becomes 16,384 x 40/32,768 x 20 = 655,360. In both cases, the total density are the same.

相關(guān)PDF資料	PDF描述
IDT72T20128L5BBI	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20128L6BB	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20128L6BBI	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20128L7BB	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20128L7BBI	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
IDT72T20128L6-7BB	功能描述:IC FIFO 1KX20 2.5V 6-7NS 208BGA RoHS:否類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步存儲(chǔ)容量:256（64 x 4）數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔封裝/外殼:24-DIP（0.300"，7.62mm）供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件其它名稱:74F433
IDT72T2098L10BB	功能描述:IC FIFO 262X20 2.5V 10NS 208BGA RoHS:否類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步存儲(chǔ)容量:256（64 x 4）數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔封裝/外殼:24-DIP（0.300"，7.62mm）供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件其它名稱:74F433
IDT72T2098L4BB	功能描述:IC FIFO 262X20 2.5V 4NS 208BGA RoHS:否類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步存儲(chǔ)容量:256（64 x 4）數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔封裝/外殼:24-DIP（0.300"，7.62mm）供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件其它名稱:74F433
IDT72T2098L5BB	功能描述:IC FIFO 262X20 2.5V 5NS 208BGA RoHS:否類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步存儲(chǔ)容量:256（64 x 4）數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔封裝/外殼:24-DIP（0.300"，7.62mm）供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件其它名稱:74F433
IDT72T2098L6-7BB	功能描述:IC FIFO 262X20 2.5V 6-7NS 208BGA RoHS:否類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步存儲(chǔ)容量:256（64 x 4）數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔封裝/外殼:24-DIP（0.300"，7.62mm）供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件其它名稱:74F433

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