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參數(shù)資料
| 型號： | IDT72T20128L5BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 2.5伏高速TeraSync⑩復員/特別提款權先進先出20-BIT/10-BIT配置 |
| 文件頁數(shù)： | 6/51頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IDT72T20128L5BBI |
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6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PIN DESCRIPTION
Symbol &
Pin No.
D
0
-D
19
(See Pin No.
table for details)
EF
/
OR
(M14)
Data Inputs
HSTL-LVTTL Data inputs for a 20-, or 10-bit bus. When using 10- bit mode, the unused input pins are in a dont care
INPUT
state. The data bus is sampled on both rising and falling edges of WCLK when
WEN
is enabled and DDR
Mode is enabled or on the rising edges of WCLK only in SDR Mode.
HSTL-LVTTL In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is
OUTPUT
empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available
at the outputs.
HSTL-LVTTL Read Clock Echo output, must be equal to or faster than the Qn data outputs.
OUTPUT
HSTL-LVTTL Read Enable Echo output, used in conjunction with ERCLK.
OUTPUT
HSTL-LVTTL In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO memory is
OUTPUT
empty. In FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available
for writing to the FIFO memory.
Empty Flag/
Output Ready
ERCLK
(L16)
EREN
(K16)
FF
/
IR
(H3)
Echo Read
Clock
Echo Read
Enable
Full Flag/
Input Ready
FSEL0
(1)
(J3)
FSEL1
(1)
(J2)
FWFT
(G2)
HSTL
(1)
(B7)
IW
(1)
(K1)
MARK
(E14)
Flag Select Bit 0
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
During Master Reset, this input along with FSEL1 will select the default offset values for the programmable
flags
PAE
and
PAF
. There are four possible settings available.
During Master Reset, this input along with FSEL0 will select the default offset values for the programmable
flags
PAE
and
PAF
. There are four possible settings available.
During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in
DDR mode. In SDR mode, the first word will always fall through on the rising edge.
This input pin is used to select HSTL or 2.5V LVTTL device operation. If HSTL inputs are required, this
input must be tied HIGH, otherwise it should be tied LOW.
During Master Reset, this pin, along with OW selects the bus width of the read and write port.
INPUT
HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmt
INPUT
operation will reset the read pointer to this position. There is an unlimted number to times to set the mark
location, but only the most recent location marked will be acknowledged.
HSTL-LVTTL
MRS
initializes the read and write pointers to zero and sets the output registers to all zeros. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
programmable flag default settings, and single or double data clock mode.
HSTL-LVTTL When HIGH, data outputs Q
0
-Q
19
are in high impedance. When LOW, the data outputs Q
0
-Q
19
are enabled.
INPUT
No other outputs are affected by
OE
.
LVTTL
During Master Reset, this pin along with IW selects the bus width of the read and write port.
INPUT
HSTL-LVTTL
PAE
goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n, which is
OUTPUT
stored in the Empty Offset register.
PAE
goes LOW if the number of words in the FIFO memory is less than
offset n.
HSTL-LVTTL
PAF
goes HIGH if the number of free locations in the FIFO memory is more than offset m which is stored
OUTPUT
in the Full Offset register.
PAF
goes LOW if the number of free locations in the FIFO memory is less than
or equal to m
HSTL-LVTTL
PRS
initializes the read and write pointers to zero and sets the output registers to all zeros. During Partial
INPUT
Reset, the existing mode (IDT standard or FWFT) and programmable flag settings are not affected.
HSTL-LVTTL Data outputs for a 20-, or 10-bit bus. When in 10- bit mode, the unused output pins should not be connected.
OUTPUT
The output data is clocked on both rising and falling edges of RCLK when
REN
is enabled and DDR Mode
is enabled or on the rising edges of RCLK only in SDR Mode.
HSTL-LVTTL Input clock when used in conjunction with
REN
for reading data fromthe FIFO memory and output
INPUT
register.
Flag Select Bit 1
First Word Fall
Through
HSTL Select
Input Width
Mark Read
Pointer for
Retransmt
Master Reset
MRS
(J1)
OE
(G15)
OW
(1)
(L3)
PAE
(L15)
Output Enable
Output Width
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
PAF
(G3)
PRS
(K3)
Q
0
-Q
19
(See Pin No.
table for details)
RCLK
(G16)
Partial Reset
Data Outputs
Read Clock
Name
I/O TYPE
Description
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20128L6-7BB | 功能描述:IC FIFO 1KX20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L10BB | 功能描述:IC FIFO 262X20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L4BB | 功能描述:IC FIFO 262X20 2.5V 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L5BB | 功能描述:IC FIFO 262X20 2.5V 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L6-7BB | 功能描述:IC FIFO 262X20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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