參數(shù)資料
型號： IDT72T20128L6BB
廠商： Integrated Device Technology, Inc.
英文描述： 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述： 2.5伏高速TeraSync⑩復(fù)員/特別提款權(quán)先進先出20-BIT/10-BIT配置
文件頁數(shù)： 14/51頁
文件大小： 496K
代理商： IDT72T20128L6BB
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Number of
Words in
FIFO
IDT72T20108
IW
≠
OW or
IW = OW = x20
IW = OW = x10
0
0
0
1 to n
(1)
1 to n
(1)
1 to n
(1)
(16,385) to (32,768-(m+1))
(32,769) to (65,536-(m+1))
(65,537) to (131,072-(m+1))
(32,768-m) to 32,767
32,768
(65,536-m) to 65,535
65,536
(131,072-m) to 131,071
131,072
IDT72T20108
IDT72T2098
IDT72T20118
IDT72T20128
0
0
1 to n
(1)
1 to n
(1)
(131,073) to (262,144-(m+1))(262,145) to (524,288-(m+1))
(262,144-m) to 262,143
(524,288-m) to 524,287
262,144
524,288
IDT72T20118
IDT72T20128
FF
PAF PAE
EF
H
H
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
IDT72T2098
5996 drw05
TABLE 5
STATUS FLAGS FOR FWFT MODE
Number of
Words in
FIFO
IDT72T20108
IW
≠
OW or
IW = OW = x20
IW = OW = x10
0
0
0
1 to n
(1)
1 to n
(1)
1 to n
(1)
(16,386) to (32,764-(m+1))
(32,770) to (65,537-(m+1))
(65,538) to (131,073-(m+1))
(32,764-m) to 32,768
(65,537-m) to 65,536
(131,073-m) to 131,072
32,769
65,537
131,073
IDT72T20108
IDT72T2098
IDT72T20118
IDT72T20128
0
0
1 to n
(1)
1 to n
(1)
(131,074) to (262,145-(m+1)) (262,146) to (524,289-(m+1))
(262,145-m) to 262,144
(524,289-m) to 524,288
262,145
524,289
IDT72T20118
IDT72T20128
IR
PAF PAE
OR
L
H
L
H
L
H
L
L
L
H
H
L
L
H
L
L
H
H
L
L
IDT72T2098
TABLE 4
STATUS FLAGS FOR IDT STANDARD MODE
NOTE:
1. See table 3 for values for n, m
NOTE:
1. See table 3 for values for n, m
2. Number of Words in FIFO = FIFO Depth + Output Register.
3. FWFT mode available only in Single Data Rate mode.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T2098/
72T20108/72T20118/72T20128 have internal registers for these offsets.
There are four selectable default offset values during Master Reset. These offset
values are shown in Table 3. The offset values can also be programmed serially
into the FIFO. To load offset values, set
SEN
LOW and the rising edge of SCLK
IDT72T2098, 72T20108, 72T20118, 72T20128
FSEL1
FSEL0
H
L
H
L
Offsets n,m
255
127
63
7
H
H
L
L
TABLE 3 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE
.
2. m= full offset for
PAF
.
will load data fromthe SI input into the offset registers. SCLK runs at a nomnal
speed of 10MHz at the maximum The programmng sequence starts with one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. The total number of bits per device is listed in Figure
3,
Programmable Flag Offset Programmng Sequence.
See Figure 25,
Loading of Programmable Flag Registers
, for the timng diagramfor this mode.
The
PAE
and
PAF
can show a valid status only after the complete set of bits (for
all offset registers) has been entered. The registers can be reprogrammed as
long as the complete set of new offset bits is entered.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Simlar to loading offset values, set
SREN
LOW and
the rising edge of SCLK will send data fromthe offset registers out to the SO output
port. When initializing a read to the offset registers, data will be read starting from
the first location in the register, regardless of where it was last read.
Figure 3,
Programmable Flag Offset Programmng Sequence
, summarizes
the control pins and sequence for programmng offset registers and reading and
writing into the FIFO.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset. Valid programmng ranges are from0 to D-1.
相關(guān)PDF資料
PDF描述
IDT72T20128L6BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20128L7BB 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20128L7BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T2098 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T2098L10BB 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T2098L10BB 功能描述:IC FIFO 262X20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T2098L4BB 功能描述:IC FIFO 262X20 2.5V 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T2098L5BB 功能描述:IC FIFO 262X20 2.5V 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T2098L6-7BB 功能描述:IC FIFO 262X20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36105L10BB 功能描述:IC FIFO 131X18 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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