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參數(shù)資料
| 型號(hào)： | IDT72T20128L7BB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 2.5伏高速TeraSync⑩復(fù)員/特別提款權(quán)先進(jìn)先出20-BIT/10-BIT配置 |
| 文件頁數(shù)： | 17/51頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IDT72T20128L7BB |
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17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 – Dn)
Data inputs for 20-bit wide data, (D
0
– D
19
), or data inputs for 10-bit wide
data (D
0
– D
9
).
CONTROLS:
MASTER RESET (
MRS
)
A Master Reset is accomplished whenever the
MRS
input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAMarray.
PAE
will go LOW and
PAF
will go HIGH.
If FWFT is LOW during Master Reset then IDT Standard mode along with
EF
and
FF
are selected.
EF
will go LOW and
FF
will go HIGH, If FWFT is
HIGH, then the First Word Fall Through (FWFT) mode, along with
IR
and
OR
are selected.
OR
will go HIGH and
IR
will go LOW.
All control settings such as OW, IW,
WSDR
,
RSDR
, FSEL0 and FSEL1 are
defined during the Master Reset cycle.
During a Master Reset the output register is initialized to all zeros. A Master
Reset is required after power up before a write operation can take place.
MRS
is asynchronous.
See Figure 8,
Master Reset Timng
, for the relevant timng diagram
PARTIAL RESET (
PRS
)
A Partial Reset is accomplished whenever the
PRS
input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAMarray.
PAE
goes LOW and
PAF
goes
HIGH.
Whichever mode was active at the time of Partial Reset will remain active
after Partial Reset. If IDT Standard Mode is active, then
FF
will go HIGH and
EF
will go LOW. If the First Word Fall Through mode is active, then
OR
will go
HIGH and
IR
will go LOW.
Following Partial Reset, all values held in the offset registers remain un-
changed. The output register is initialized to all zeroes.
PRS
is asynchronous.
Partial Reset is useful for resetting the read and write pointers to zero without
affecting the values of the programmable flag offsets and the timng mode of the
FIFO.
See Figure 9,
Partial Reset Timng
, for the relevant timng diagram
RETRANSMIT (
RT
)
The Retransmt (
RT
) input is used in conjunction with the MARK input.
Together they provide a means by which data previously read out of the FIFO
can be reread any number of times. When the retransmt operation is selected
(i.e. after data has been marked), a rising edge on RCLK while
RT
is LOW will
reset the read pointer back to the memory location set by the user via the
MARK input.
If IDT Standard mode has been selected, the
EF
flag will go LOW on the
rising edge of RCLK that retransmt was initiated (i.e. rising edge of RCLK
while
RT
is LOW).
EF
will go back to HIGH on the next rising edge of RCLK,
which signifies that retransmt setup is complete. The next read operation will
access data fromthe “marked” memory location.
Subsequent retransmt operations may be performed, each time the read
pointer returning to the “marked” location. See Figure 23,
Retransmt from
Mark in Double Data Rate Mode (IDT Standard Mode)
for the relevant timng
diagram
If FWFT mode has been selected, the
OR
flag will go HIGH on the rising
edge of RCLK that retransmt was initiated.
OR
will return LOW on the next
rising edge of RCLK, which signifies that retransmt setup is complete. Under
FWFT mode, the contents in the marked memory location will be loaded onto
the output register on the next rising edge of RCLK. To access all subsequent
data, a read operation will be required.
Subsequent retransmt operations may be performed, each time the read
pointer returning to the “marked” location. See Figure 24,
Retransmt from
Mark (FWFT Mode)
for the relevant timng diagram
MARK
The MARK input is used to select Retransmt mode of operation. On a rising
edge of RCLK while MARK is HIGH will mark the memory location of the data
currently present on the output register, in addition placing the device in
retransmt mode. Note, there must be a mnimumof 1280 bits (or 160 bytes) of
data between the write pointer and mark location. That is, 20 bits x64 for the
x20 mode and 10 bits x128 for the x10 mode. Also, once the MARK is set, the
write pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmt data.
The MARK input must remain HIGH during the whole period of retransmt
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmt mode and into normal mode. Any number of MARK locations can
be set during FIFO operation, only the last marked location taking effect. Once
a mark location has been set the write pointer cannot be incremented past this
marked location. During retransmt mode write operations to the device may
continue without hindrance.
FIRST WORD FALL THROUGH (FWFT)
During Master Reset, the state of the FWFT input determnes whether the
device will operate in IDT Standard mode or First Word Fall Through (FWFT)
mode.
If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (
EF
) to indicate whether or not
there are any words present in the FIFO memory. It also uses the Full Flag
function (
FF
) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read fromthe FIFO, including
the first, must be requested using the Read Enable (
REN
) and RCLK.
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR
) to indicate whether or not there
is valid data at the outputs (Qn) to be read. It also uses Input Ready (
IR
) to
indicate whether or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn after
three RCLK rising edges, bringing
REN
LOW is not necessary. Subsequent
words must be accessed using the Read Enable (
REN
) and RCLK. Note that
FWFT mode can only be used when the device is configured to Single Data
Rate (SDR) mode.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising and/or falling edge of the WCLK input.
If the Write Single Data Rate (
WSDR
) pin is selected, data will be written only
on the rising edge of WCLK, provided that
WEN
and
WCS
are LOW. If the
WSDR
is not selected, data will be written on both the rising and falling edge of
WCLK, provided that
WEN
and
WCS
are LOW. Data setup and hold times
must be met with respect to the LOW-to-HIGH transition of the WCLK. It is
permssible to stop the WCLK. Note that while WCLK is idle, the
FF
,
IR
, and
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| IDT72T20128L7BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
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| IDT72T2098L10BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L10BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L4BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT72T2098L10BB | 功能描述:IC FIFO 262X20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L4BB | 功能描述:IC FIFO 262X20 2.5V 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L5BB | 功能描述:IC FIFO 262X20 2.5V 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T2098L6-7BB | 功能描述:IC FIFO 262X20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36105L10BB | 功能描述:IC FIFO 131X18 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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