參數(shù)資料
型號(hào): IDT72T2098L4BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述: 32K X 20 OTHER FIFO, 3.2 ns, PBGA208
封裝: 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù): 8/51頁(yè)
文件大?。?/td> 496K
代理商: IDT72T2098L4BB
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PIN NUMBER TABLE
Symbol
Name
I/O TYPE
Pin Number
D
0-19
Data Inputs
HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7,
INPUT
D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3
HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14
OUTPUT
Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10
INPUT
A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2)
INPUT
A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13),
P(10-13), T(15,16)
INPUT
A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9),
P(4,8,9), R(8,9), T(8,9)
A3, B(1-3,15,16), C(1,2,14-16), D(1-3,14-16), E(1,15,16), K2, M(1-3,15,16), N(1-3,14-16), P(1,2,14-16),
R(1,2,15,16)
Q
0-19
Data Outputs
V
CC
V
DDQ
+2.5V Supply
O/P Rail Voltage
GND
Ground Pin
DNC
Do Not Connect
PIN DESCRIPTION (CONTINUED)
Symbol &
Name
Pin No.
WSDR
(1)
Write Single Data
(L1)
Rate
I/O TYPE
Description
LVTTL
INPUT
When LOW, this input pin sets the write port to Single Data Clock mode. When HIGH, the write port will
operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during
operation.
There are V
CC
supply inputs and must be connected to the 2.5V supply rail.
V
CC
(See below)
V
DDQ
(See below)
GND
(See below)
Vref
(T3)
+2.5V Supply
INPUT
O/P Rail Voltage
INPUT
This pin should be tied to the desired voltage rail for providing power to the output drivers. Nomnally 1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
These are Ground pins are for the core device and must be connected to the GND rail.
Ground Pin
INPUT
Reference
Voltage
INPUT
This is a Voltage Reference input and must be connected to a voltage level determned in the Recommended
DC Operating Conditions section. This provides the reference voltage when using HSTL class inputs.
If HSTL class inputs are not being used, this pin can be left floating.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 24-27 and Figures 5-7.
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