參數(shù)資料
型號(hào)： IDT72T2098L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述： 32K X 20 OTHER FIFO, 3.6 ns, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 16/51頁(yè)
文件大?。?/td> 496K
代理商： IDT72T2098L5BB
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
RETRANSMIT FROMMARK OPERATION
The Retransmt fromMark feature allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into retransmt mode
that will “mark” a beginning word and also set a pointer that will prevent
ongoing FIFO write operations fromover-writing retransmt data. The retrans-
mt data can be read repeatedly any number of times fromthe “marked”
position. The FIFO can be taken out of retransmt mode at any time to allow
normal device operation. The “mark” position can be selected any number of
times, each selection over-writing the previous mark location.
In Double Data Rate, data is always marked in pairs. That is, the unit of data
read on the rising and falling edge of WCLK. If the data marked was read on
the falling edge of RCLK, then the marked data will be the unit of data read from
the rising and falling edge of that particular RCLK edge. Refer to Figure 23,
Retransmt fromMark in Double Data Rate Mode
, for the timng diagramin
this mode. Retransmt operation is available in both IDT standard and FWFT
modes.
During IDT standard mode the FIFO is put into retransmt mode by a Low-
to-High transition on RCLK when the MARK input is HIGH and
EF
is HIGH.
The rising RCLK edge marks the data present in the FIFO output register as
the first retransmt data. Again, the data is marked in pairs. Thus if the data
marked was read on the falling edge of RCLK, the first part of retransmt will
read out the data read on the rising edge of RCLK, followed by the data on the
falling edge (the marked data). The FIFO remains in retransmt mode until a
rising edge on RCLK occurs while MARK is LOW.
Once a marked location has been set, a retransmt can be initiated by a
rising edge on RCLK while the Retransmt input (
RT
) is LOW.
REN
must be
HIGH (reads disabled) before bringing
RT
LOW. The device indicates the start
of retransmt setup by setting
EF
LOW, also preventing reads. When
EF
goes
HIGH, retransmt setup is complete and read operations may begin starting
with the first unit of data at the MARK location. Since IDT standard mode is
selected, every word read including the first “marked” word following a re-
transmt setup requires a LOW on
REN
.
Note, write operations may continue as normal during all retransmt functions,
however write operations to the “marked” location will be prevented. See Figure
23,
Retransmt fromMark in Double Data Rate Mode
, for the relevant timng
diagram
During FWFT mode the FIFO is put into retransmt mode by a rising RCLK
edge when the MARK input is HIGH and
OR
is LOW. The rising RCLK edge
marks the data present in the FIFO output register as the first retransmt data.
The data is marked in pairs. The FIFO remains in retransmt mode until a
rising RCLK edge occurs while MARK is LOW.
Once a marked location has been set, a retransmt can be initiated by a
rising RCLK edge while the Retransmt input (
RT
) is LOW.
REN
must be
HIGH (reads disabled) before bringing
RT
LOW. The device indicates the
start of retransmt setup by setting
OR
HIGH, preventing read operations.
When
OR
goes LOW, retransmt setup is complete and on the next rising
RCLK edge (
RT
goes HIGH), the contents of the first retransmt location are
loaded onto the output register. Since FWFT mode is selected, the first word
appears on the outputs regardless of
REN
, a LOW on
REN
is not required for
the first word. Reading all subsequent words requires a LOW on
REN
to
enable the rising RCLK edge. See Figure 24,
Retransmt fromMark (FWFT
mode)
for the relevant timng diagram
Before a retransmt can be performed, there must be at least 1280 bits (or
160 bytes) of data between the write pointer and mark location.That is, 20 bits
x64 for the x20 mode and 10 bits x128 for the x10 mode. Also, once the Mark
is set, the write pointer will not increment past the marked location, preventing
overwrites of retransmt data.
HSTL/LVTTL I/O
This device supports both LVTTL and HSTL logic levels on the input and
output signals. If LVTTL is desired, a LOW on the HSTL pin will set the inputs
and outputs to LVTTL mode. If HSTL is desired, a HIGH on the HSTL pin will
set the inputs and outputs to HSTL mode. VREF is the input voltage reference
used in HSTL mode. Typically a logic HIGH in HSTL would be Vref + 0.2V and
a logic LOW would be VREF – 0.2V. Table 6 illustrates which pins are and are
not associated with this feature. Note that all “Static Pins” must be tied to Vcc or
GND. These pins are LVTTL only and are purely device configuration pins.
HSTL SELECT
STATIC PINS
LVTTL ONLY
HIGH = HSTL
LOW = LVTTL
Write Port
Dn (I/P)
WCLK (I/P)
WEN
(I/P)
WCS
(I/P)
Read Port
Signal Pins
Static Pins
IW (I/P)
OW (I/P)
HSTL (I/P)
FSEL1 (I/P)
FSEL0 (I/P)
FWFT (I/P)
WSDR
(I/P)
RSDR
(I/P)
Qn (O/P)
RCLK (I/P)
REN
(I/P)
RCS
(I/P)
MARK (I/P)
OE
(I/P)
RT
(I/P)
EF
/
OR
(O/P)
PAF
(O/P)
PAE
(O/P)
FF
/
IR
(O/P)
ERCLK (O/P)
EREN
(O/P)
SCLK (I/P)
SI (I/P)
SO (O/P)
MRS
(I/P)
PRS
(I/P)
TCK (I/P)
TMS (I/P)
TRST
(I/P)
TDI (I/P)
TDO (O/P)
SEN
(I/P)
SREN
(I/P)
TABLE 6 — I/O CONFIGURATION
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T2098L6-7BB 功能描述:IC FIFO 262X20 2.5V 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36105L10BB 功能描述:IC FIFO 131X18 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36105L4-4BB 功能描述:IC FIFO 131X18 4-4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36105L5BB 功能描述:IC FIFO 131X18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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