參數(shù)資料
型號： IDT72T2098L7BB
廠商： Integrated Device Technology, Inc.
英文描述： 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述： 2.5伏高速TeraSync⑩復(fù)員/特別提款權(quán)先進(jìn)先出20-BIT/10-BIT配置
文件頁數(shù)： 15/51頁
文件大?。?/td> 496K
代理商： IDT72T2098L7BB
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Figure 3. Programmable Flag Offset Programming Sequence
Write Memory (DDR)
Write Memory (SDR)
Read Memory (DDR)
No Operation
5996 drw06
X
1
1
X
X
X
0
1
X
0
1
X
X
X
0
1
X
1
1
X
X
X
1
0
X
1
0
X
X
X
1
0
X
X
X
X
1
1
X
X
X
Read Memory (SDR)
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
x10 to x10 Mode
All Other Modes
WCLK
RCLK
X
WSDR
X
X
RSDR
X
X
SEN
0
1
X
SREN
1
0
SCLK
X
X
WEN
1
1
REN
1
1
x10 to x10 Mode
All Other Modes
Serial Write to registers:
In SDR Mode:
32 bits for the IDT72T2098
34 bits for the IDT72T20108
36 bits for the IDT72T20118
38 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Write to registers:
In SDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read From registers:
In SDR Mode:
32 bits for the IDT72T2098
34 bits for the IDT72T20108
36 bits for the IDT72T20118
38 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In SDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Write to registers:
In DDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Write to registers:
In DDR Mode:
28 bits for the IDT72T2098
30 bits for the IDT72T20108
32 bits for the IDT72T20118
34 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In DDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In DDR Mode:
28 bits for the IDT72T2098
30 bits for the IDT72T20108
32 bits for the IDT72T20118
34 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
NOTES:
1. The programmng sequence applies to both IDT Standard and FWFT modes.
2. When the input or output ports are in DDR mode, the depth is reduced by half but the overall density remains the same. For example, the IDT72T2098 in SDR mode is
32,768 x 20/65,536 x 10 = 655,360, in DDR mode the configuration becomes 16,384 x 40/32,768 x 20 = 655,360. In both cases, the total density are the same.
相關(guān)PDF資料
PDF描述
IDT72T2098L7BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20108L10BB 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20108L10BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20108L4BB 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20108L4BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
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