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參數(shù)資料
| 型號： | IDT72T36115L5BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS |
| 中文描述： | 128K X 36 OTHER FIFO, 3.6 ns, PBGA240 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-240 |
| 文件頁數(shù)： | 4/57頁 |
| 文件大?。?/td> | 556K |
| 代理商： | IDT72T36115L5BBI |
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4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DESCRIPTION:
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are exceptionally deep, extrememy high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write
controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer
several key user benefits:
Flexible x36/x18/x9 Bus-Matching on both read and write ports
A user selectable MARK location for retransmt
User selectable I/O structure for HSTL or LVTTL
Asynchronous/Synchronous translation on the read or write ports
The first word data latency period, fromthe time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determned by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (
WEN
) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when
WEN
is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN
input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (
REN
) input. Data
is read fromthe FIFO on every rising edge of RCLK when
REN
is asserted.
During Asynchronous operation only the RD input is used to read data fromthe
FIFO. Data is read on a rising edge of RD, the
REN
input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the
RCS
should be
tied LOW and the
OE
input used to provide three-state control of the outputs, Qn.
The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.
An Output Enable (
OE
) input is provided for three-state control of the outputs.
A Read Chip Select (
RCS
) input is also provided, the
RCS
input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When
RCS
is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port,
RCS
should be enabled, held LOW.
Echo Read Enable,
EREN
and Echo Read Clock, ERCLK outputs are
provided. These are outputs fromthe read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmtted fromthe Qn outputs and the data being received by
the input device. Data read fromthe read port is available on the output bus with
respect to
EREN
and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and
EREN
outputs are non-functional when the Read
port is setup for Asynchronous mode.
The frequencies of both the RCLK and the WCLK signals may vary from0
to f
MAX
with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timng modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word frominternal memory to the data output lines.
In
FWFT mode,
the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN
for access. The state of
the FWFT/SI input during Master Reset determnes the timng mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timng mode permts depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF
/
OR
(Empty Flag or Output Ready),
FF
/
IR
(Full Flag or Input Ready),
HF
(Half-full Flag),
PAE
(Programmable
Almost-Empty flag) and
PAF
(Programmable Almost-Full flag). The
EF
and
FF
functions are selected in IDT Standard mode. The
IR
and
OR
functions are
selected in FWFT mode.
HF
,
PAE
and
PAF
are always available for use,
irrespective of timng mode.
PAE
and
PAF
can be programmed independently to switch at any point in
memory. Programmable offsets determne the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that
PAE
can be set to switch at a predefined number of locations
fromthe empty boundary and the
PAF
threshold can also be set at simlar
predefined values fromthe full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and
LD
pins.
For serial programmng,
SEN
together with
LD
on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programmng,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel fromQ
n
regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (
MRS
) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (
PRS
) also sets the read and write pointers to the first
location of the memory. However, the timng mode, programmable flag
programmng method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timng
mode and offsets in effect.
PRS
is useful for resetting a device in md-operation,
when reprogrammng programmable flags would be undesirable.
It is also possible to select the timng mode of the
PAE
(Programmable Almost-
Empty flag) and
PAF
(Programmable Almost-Full flag) outputs. The timng
modes can be set to be either asynchronous or synchronous for the
PAE
and
PAF
flags.
If asynchronous
PAE
/
PAF
configuration is selected, the
PAE
is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Simlarly, the
PAF
is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE
/
PAF
configuration is selected , the
PAE
is asserted and
updated on the rising edge of RCLK only and not WCLK. Simlarly,
PAF
is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during MasterReset by the state of the Programmable Flag
Mode (PFM) pin.
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參數(shù)描述 |
|---|---|
| IDT72T36115L6-7BB | 功能描述:IC FIFO 131KX36 6-7NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36125L10BB | 功能描述:IC FIFO 524X18 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36125L4-4BB | 功能描述:IC FIFO 524X18 4-4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36125L4-4BBG | 功能描述:IC FIFO 524X18 4-4NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36125L5BB | 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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