參數(shù)資料
型號(hào)： IDT72T36115L6BBI
廠商： Integrated Device Technology, Inc.
英文描述： TRANS PNP 50VCEO 2A TO-126
中文描述： 2.5伏高速TeraSyncTM FIFO的36位配置
文件頁(yè)數(shù)： 17/57頁(yè)
文件大?。?/td> 556K
代理商： IDT72T36115L6BBI
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the
LD
(Load) pin. During Master Reset, the state of the
LD
input determnes
whether serial or parallel flag offset programmng is enabled. A HIGH on
LD
during Master Reset selects serial loading of offset values. A LOW on
LD
during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q
0
-Qn, regardless of the programmng mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3,
Programmable Flag Offset Programmng Sequence
, summaries
the control pins and sequence for both serial and parallel programmng modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programmng has
been selected. Valid programmng ranges are from0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timng for
PAF
and
PAE
flags
by use of the PFMpin.
If synchronous
PAF
/
PAE
configuration is selected (PFM HIGH during
MRS
), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Simlarly,
PAE
is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timng diagrams, see Figure 23 for synchronous
PAF
timng and Figure 24 for synchronous
PAE
timng.
If asynchronous
PAF
/
PAE
configuration is selected (PFM LOW during
MRS
), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH transition of RCLK. Simlarly,
PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timng diagrams, see
Figure 25 for asynchronous
PAF
timng and Figure 26 for asynchronous
PAE
timng.
IDT72T3645, 72T3655
FSEL1
H
L
L
H
L
H
L
H
*
LD
L
L
L
L
H
H
H
H
FSEL0
L
H
L
H
L
L
H
H
Offsets n,m
511
255
127
63
31
15
7
3
*
LD
H
L
IDT72T3665,72T3675,72T3685,72T3695, 72T36105,
72T36115, 72T36125
*
LD
FSEL1
H
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
FSEL1
X
X
FSEL0
X
X
Program Mode
Serial
(3)
Parallel
(4)
FSEL0
L
L
H
L
H
L
H
H
Offsets n,m
1,023
511
255
127
63
31
15
7
*
LD
H
L
FSEL1
X
X
FSEL0
X
X
Program Mode
Serial
(3)
Parallel
(4)
*
THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROMTHE FIFO MEMORY.
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE
.
2. m= full offset for
PAF
.
3. As well as selecting serial programmng mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programmng mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
相關(guān)PDF資料
PDF描述
IDT72T36125L5BBI 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T36125L6BBI 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T51253L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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IDT72T36125L4-4BB 功能描述:IC FIFO 524X18 4-4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36125L4-4BBG 功能描述:IC FIFO 524X18 4-4NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36125L5BB 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36125L5BBG 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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