參數(shù)資料
型號(hào)： IDT72T3655L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
中文描述： 2K X 36 OTHER FIFO, 3.6 ns, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 20/57頁(yè)
文件大小： 556K
代理商： IDT72T3655L5BB
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
# of Bits Used:
10 bits for the IDT72T3645
11 bits for the IDT72T3655
12 bits for the IDT72T3665
13 bits for the IDT72T3675
14 bits for the IDT72T3685
15 bits for the IDT72T3695
16 bits for the IDT72T36105
17 bits for the IDT72T36115
18 bits for the IDT72T36125
Note: All unused bits of the
LSB & MSB are don’t care
5907 drw07
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (
PAE
)
12
13
14
15
16
17
# of Bits Used
2
3
4
5
6
7
9
10
11
12
13
14
15
16
1st Parallel Offset Write/Read Cycle
2
3
4
5
6
7
8
8
11
Interspersed
17
10
1
1
D/Q35 D/Q19
9
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (
PAF
)
12
13
14
15
16
# of Bits Used
2
3
4
5
6
7
9
10
11
12
13
14
15
16
2nd Parallel Offset Write/Read Cycle
2
3
4
5
6
7
8
8
17
11
Interspersed
17
10
1
1
9
IDT72T3645/55/65/75/85/95/105/115/125
x36 Bus Width
Non-Interspersed
Non-Interspersed
D/Q35 D/Q19
D/Q17
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (
PAE
)
9
10
11
12
13
14
15
10
11
12
13
14
9
D/Q8
Data Inputs/Outputs
# of Bits Used
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
16
15
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
FULL OFFSET (LSB) REGISTER (
PAF
)
10
11
12
13
14
15
10
11
12
13
14
9
D/Q8
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
16
15
Non-Interspersed
Interspersed
D/Q0
16
16
IDT72T3645/55/65/75/85/95/105
x18 Bus Width
D/Q17
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (
PAE
)
9
10
11
12
13
14
15
10
11
12
13
14
9
D/Q8
Data Inputs/Outputs
# of Bits Used
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
EMPTY OFFSET (MSB) REGISTER (
PAE
)
Data Inputs/Outputs
17
17
16
15
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
D/Q17D/Q16
Data Inputs/Outputs
FULL OFFSET (LSB) REGISTER (
PAF
)
10
11
12
13
14
15
10
11
12
13
14
9
D/Q8
Data Inputs/Outputs
FULL OFFSET (MSB) REGISTER (
PAF
)
3rd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
4th Parallel Offset Write/Read Cycle
D/Q17D/Q16
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
16
15
17
17
Non-Interspersed
Interspersed
D/Q0
D/Q0
D/Q0
16
16
IDT72T36115/72T36125
x18 Bus Width
18
18
18
18
18
18
18
18
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE
)
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (
PAE
)
3rd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (
PAE
)
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (
PAF
)
D/Q0
9
10
11
12
13
14
15
16
D/Q0
1
2
3
4
5
6
7
8
D/Q0
17
5th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (
PAF
)
D/Q0
9
10
11
12
13
14
15
16
6th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (
PAF
)
D/Q0
17
IDT72T36115/72T36125
x9 Bus Width
18
18
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE
)
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (
PAE
)
3rd Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (
PAF
)
D/Q0
9
10
11
12
13
14
15
16
D/Q0
1
2
3
4
5
6
7
8
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (
PAF
)
D/Q0
9
10
11
12
13
14
15
16
IDT72T3645/55/65/75/85/95/105
x9 Bus Width
NOTE:
1. Consecutive reads of the offset registers is not permtted. The read operation must be disabled for a mnimumof one RCLK cycle in between offset register accesses. (Please
refer to Figure 22,
Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
for more details).
相關(guān)PDF資料
PDF描述
IDT72T3665L5BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T3685L5BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T3695L5BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T36125L5BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T3645L4BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T3655L5BBI 功能描述:IC FIFO 2048X36 5NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T3655L6-7BB 功能描述:IC FIFO 2048X36 6-7NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72T3665L4-4BB 功能描述:IC FIFO 4096X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T3665L4-4BBG 功能描述:IC FIFO 4096X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T3665L5BB 功能描述:IC FIFO 4096X36 5NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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