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    參數(shù)資料
    

    


    


    
型號(hào)：
IDT72T3695L4BB

    

    
廠商：
Integrated Device Technology, Inc.

    

    
英文描述：
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

    

    
中文描述：
2.5伏高速TeraSyncTM FIFO的36位配置

    

    
文件頁數(shù)：
16/57頁

    

    
文件大?。?/td>
556K

    

    
代理商：
IDT72T3695L4BB


    

    

    

	
    
    
    

    
    
	
    16
    COMMERCIAL  AND  INDUSTRIAL
    TEMPERATURE  RANGES
    IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
     36-BIT FIFO
    1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
    FUNCTIONAL DESCRIPTION
    TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
    (FWFT) MODE
    The IDT72T3645/55/65/75/85/95/105/115/125 support two different tim-
    ing modes of operation: IDT Standard mode or First Word Fall Through
    (FWFT) mode. The selection of which mode will operate is determned during
    Master Reset, by the state of the FWFT/SI input.
    If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
    will be selected. This mode uses the Empty Flag
    (
    EF
    ) to indicate whether or not
    there are any words present in the FIFO. It also uses the Full Flag function (
    FF
    )
    to indicate whether or not the FIFO has any free space for writing. In IDT
    Standard mode, every word read fromthe FIFO, including the first, must be
    requested using the Read Enable (
    REN
    ) and RCLK.
    If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
    selected. This mode uses Output Ready (
    OR
    ) to indicate whether or not there
    is valid data at the data outputs (Q
    n)
    . It also uses Input Ready (
    IR
    ) to indicate
    whether or not the FIFO has any free space for writing. In the FWFT mode, the
    first word written to an empty FIFO goes directly to Q
    n
     after three RCLK rising
    edges, 
    REN
     = LOW is not necessary. Subsequent words must be accessed
    using the Read Enable (
    REN
    ) and RCLK.
    Various signals, both input and output signals operate differently depending
    on which timng mode is in effect.
    IDT STANDARD MODE
    In this mode, the status flags, 
    FF
    , 
    PAF
    , 
    HF
    , 
    PAE
    , and 
    EF
     operate in the
    manner outlined in Table 3. To write data into to the FIFO, Write Enable (
    WEN
    )
    must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
    on subsequent transitions of the Write Clock (WCLK). After the first write is
    performed, the Empty Flag (
    EF
    ) will go HIGH. Subsequent writes will continue
    to fill up the FIFO. The Programmable Almost-Empty flag (
    PAE
    ) will go HIGH
    after n + 1 words have been loaded into the FIFO, where n is the empty offset
    value. The default setting for these values are stated in the footnote of Table 2.
    This parameter is also user programmable. See section on Programmable Flag
    Offset Loading.
    If one continued to write data into the FIFO, and we assumed no read
    operations were taking place, the Half-Full flag (
    HF
    ) would toggle to LOW once
    the 513rd word for IDT72T3645, 1,025th word for IDT72T3655, 2,049th word
    for IDT72T3665, 4,097th word for IDT72T3675, 8,193th word for the
    IDT72T3685, 16,385th word for the IDT72T3695, 32,769th word for the
    IDT72T36105, 65,537th word for the IDT72T36115 and 131,073rd word for
    the IDT72T36125, respectively was written into the FIFO. Continuing to write
    data into the FIFO will cause the Programmable Almost-Full flag (
    PAF
    ) to go
    LOW. Again, if no reads are performed, the 
    PAF
     will go LOW after (1,024-m
    writes for the IDT72T3645, (2,048-m writes for the IDT72T3655, (4,096-m
    writes for the IDT72T3665, (8,192-m writes for the IDT72T3675, (16,384-m
    writes for the IDT72T3685, (32,768-m writes for the IDT72T3695, (65,536-m
    writes for the IDT72T36105, (131,072-m writes for the IDT72T36115 and
    (262,144-m writes for the IDT72T36125. The offset “m” is the full offset value.
    The default setting for these values are stated in the footnote of Table 2. This
    parameter is also user programmable. See section on Programmable Flag
    Offset Loading.
    When the FIFO is full, the Full Flag (
    FF
    ) will go LOW, inhibiting further write
    operations. If no reads are performed after a reset, 
    FF
     will go LOW after D writes
    to the FIFO. D = 1,024 writes for the IDT72T3645, 2,048 writes for the
    IDT72T3655, 4,096 writes for the IDT72T3665, 8,192 writes for the IDT72T3675,
    16,384 writes for the IDT72T3685, 32,768 writes for the IDT72T3695,  65,536
    writes for the IDT72T36105, 131,072 writes for the IDT72T36115 and 262,144
    writes for the IDT72T36125, respectively.
    If the FIFO is full, the first read operation will cause 
    FF
     to go HIGH.
    Subsequent read operations will cause 
    PAF
     and 
    HF
     to go HIGH at the conditions
    described in Table 3. If further read operations occur, without write operations,
    PAE
     will go LOW when there are n words in the FIFO, where n is the empty
    offset value. Continuing read operations will cause the FIFO to become empty.
    When the last word has been read fromthe FIFO, the 
    EF
     will go LOW inhibiting
    further read operations. 
    REN
     is ignored when the FIFO is empty.
    When configured in IDT Standard mode, the 
    EF
     and 
    FF
     outputs are double
    register-buffered outputs.
    Relevant timng diagrams for IDT Standard mode can be found in Figure
    11, 12, 13 and 18.
    FIRST WORD FALL THROUGH MODE (FWFT)
    In this mode, the status flags, 
    IR
    , 
    PAF
    , 
    HF
    , 
    PAE
    , and 
    OR
     operate in the
    manner outlined in Table 4. To write data into to the FIFO, 
    WEN
     must be LOW.
    Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
    transitions of WCLK. After the first write is performed, the Output Ready (
    OR
    )
    flag will go LOW. Subsequent writes will continue to fill up the FIFO. 
    PAE
     will go
    HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
    offset value. The default setting for these values are stated in the footnote of
    Table 2. This parameter is also user programmable. See section on Program-
    mable Flag Offset Loading.
    If one continued to write data into the FIFO, and we assumed no read
    operations were taking place, the 
    HF
     would toggle to LOW once the 514th word
    for the IDT72T3645, 1,026th word for the IDT72T3655, 2,050th word for the
    IDT72T3665, 4,098th word for the IDT72T3675, 8,194th word for the
    IDT72T3685, 16,386th word for the IDT72T3695, 32,770th word for the
    IDT72T36105, 65,538th word for the IDT72T36115 and 131,074th word for
    the IDT72T36125, respectively was written into the FIFO. Continuing to write
    data into the FIFO will cause the 
    PAF
     to go LOW. Again, if no reads are
    performed, the 
    PAF 
    will goLOW after (1,025-m writes for the IDT72T3645,
    (2,049-m writes for the IDT72T3655, (4,097-m writes for the IDT72T3665
    and (8,193-m writes for the IDT72T3675, (16,385-m writes for the IDT72T3685,
    (32,769-m writes for the IDT72T3695, (65,537-m writes for the IDT72T36105,
    (131,073-m writes for the IDT72T36115 and (262,145-m writes for the
    IDT72T36125, where mis the full offset value. The default setting for these values
    are stated in the footnote of Table 2.
    When the FIFO is full, the Input Ready (
    IR
    ) flag will go HIGH, inhibiting further
    write operations. If no reads are performed after a reset, 
    IR
     will go HIGH after
    D writes to the FIFO.  D = 1,025 writes for the IDT72T3645, 2,049 writes for
    the IDT72T3655, 4,097 writes for the IDT72T3665 and 8,193 writes for the
    IDT72T3675,16,385 writes for the IDT72T3685, 32,769 writes for the
    IDT72T3695, 65,537 writes for the IDT72T36105, 131,073 writes for the
    IDT72T36115 and 262,145 writes for the IDT72T36125, respectively. Note
    that the additional word in FWFT mode is due to the capacity of the memory plus
    output register.
    If the FIFO is full, the first read operation will cause the 
    IR
     flag to go LOW.
    Subsequent read operations will cause the 
    PAF
     and 
    HF
     to go HIGH at the
    conditions described in Table 4. If further read operations occur, without write
    operations, the 
    PAE
     will go LOW when there are n + 1 words in the FIFO, where
    n is the empty offset value. Continuing read operations will cause the FIFO to
    become empty. When the last word has been read fromthe FIFO, 
    OR
     will go
    HIGH inhibiting further read operations. 
    REN
     is ignored when the FIFO is empty.
    When configured in FWFT mode, the 
    OR
     flag output is triple register-
    buffered, and the 
    IR
     flag output is double register-buffered.
    Relevant timng diagrams for FWFT mode can be found in Figure 14, 15,
    16 and 19.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
IDT72T36125L4BB
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

    

    
IDT72T36115L5BBI
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

    

    
IDT72T36115L6BBI
TRANS PNP 50VCEO 2A TO-126

    

    
IDT72T36125L5BBI
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

    

    
IDT72T36125L6BBI
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
IDT72T3695L5BB
功能描述:IC FIFO 32768X36 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433

    

    
IDT72T3695L5BBI
功能描述:IC FIFO 32768X36 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433

    

    
IDT72T3695L6-7BB
功能描述:IC FIFO 32768X36 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433

    

    
IDT72T40108L10BB
功能描述:IC FIFO DDR/SDR 10NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433

    

    
IDT72T40108L4BB
功能描述:IC FIFO DDR/SDR 4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433

    

    
    
    
    
	
    	
    
    
     
     
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