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參數(shù)資料
| 型號： | IDT72T3695L7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSyncTM FIFO的36位配置 |
| 文件頁數(shù)： | 27/57頁 |
| 文件大?。?/td> | 556K |
| 代理商： | IDT72T3695L7BBI |
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27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
OUTPUTS:
FULL FLAG (
FF
/
IR
)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF
) function
is selected. When the FIFO is full,
FF
will go LOW, inhibiting further write
operations. When
FF
is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS
or
PRS
),
FF
will go LOW after D writes to the FIFO
(D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the
IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115
and 262,144 for the IDT72T36125). See Figure 11,
Write Cycle and Full Flag
Timng (IDT Standard Mode)
, for the relevant timng information.
In FWFT mode, the Input Ready (
IR
) function is selected.
IR
goes LOW
when memory space is available for writing in data. When there is no longer
any free space left,
IR
goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either
MRS
or
PRS
),
IR
will go HIGH after D writes
to the FIFO (D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097
for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685,
32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the
IDT72T36115 and 262,145 for the IDT72T36125). See Figure 14,
Write
Timng (FWFT Mode)
, for the relevant timng information.
The
IR
status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IR
is one greater than needed to
assert
FF
in IDT Standard mode.
FF
/
IR
is synchronous and updated on the rising edge of WCLK.
FF
/
IR
are
double register-buffered outputs.
Note, when the device is in Retransmt mode, this flag is a comparison of the
write pointer to the marked location. This differs fromnormal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF
/
OR
)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF
)
function is selected. When the FIFO is empty,
EF
will go LOW, inhibiting further
read operations. When
EF
is HIGH, the FIFO is not empty. See Figure 12,
Read
Cycle, Empty Flag and First Word Latency Timng (IDT Standard Mode)
, for
the relevant timng information.
In FWFT mode, the Output Ready (
OR
) function is selected.
OR
goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
OR
stays LOW after the RCLK LOW to HIGH transition that shifts
the last word fromthe FIFO memory to the outputs.
OR
goes HIGH only with
a true read (RCLK with
REN
= LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until
OR
goes
LOW again. See Figure 15,
Read Timng (FWFT Mode)
, for the relevant timng
information.
EF
/
OR
is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF
is a double register-buffered output. In FWFT
mode,
OR
is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
)
The Programmable Almost-Full flag (
PAF
) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS
),
PAF
will go LOW after (D - m words are written
to the FIFO.
The
PAF
will go LOW after (1,024-m writes for the IDT72T3645,
(2,048-m writes for the IDT72T3655, (4,096-m writes for the IDT72T3665,
(8,192-m writes for the IDT72T3675, (16,384-m writes for the IDT72T3685,
(32,768-m writes for the IDT72T3695, (65,536-m writes for the IDT72T36105,
(131,072-m writes for the IDT72T36115 and (262,144-m writes for the
IDT72T36125. The offset “m” is the full offset value. The default setting for this
value is stated in the footnote of Table 3.
In FWFT mode, the
PAF
will go LOW after (1,025-m writes for the
IDT72T3645, (2,049-m writes for the IDT72T3655, (4,097-m writes for the
IDT72T3665 and (8,193-m writes for the IDT72T3675, (16,385-m writes for
the IDT72T3685, (32,769-m writes for the IDT72T3695, (65,537-m writes for
the IDT72T36105, (131,073-m writes for the IDT72T36115 and (262,145-m
writes for the IDT72T36125, where mis the full offset value. The default setting
for this value is stated in Table 4.
See Figure 23,
Synchronous Programmable Almost-Full Flag Timng (IDT
Standard and FWFT Mode)
, for the relevant timng information.
If asynchronous
PAF
configuration is selected, the
PAF
is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF
is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous
PAF
configuration is selected, the
PAF
is updated on the rising edge of WCLK. See
Figure 25,
Asynchronous Almost-Full Flag Timng (IDT Standard and FWFT
Mode)
.
Note, when the device is in Retransmt mode, this flag is a comparison of the
write pointer to the marked location. This differs fromnormal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
)
The Programmable Almost-Empty flag (
PAE
) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode,
PAE
will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE
will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24,
Synchronous Programmable Almost-Empty Flag Timng
(IDT Standard and FWFT Mode)
, for the relevant timng information.
If asynchronous
PAE
configuration is selected, the
PAE
is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE
is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous
PAE
configuration is selected, the
PAE
is updated on the rising edge of RCLK. See
Figure 26,
Asynchronous Programmable Almost-Empty Flag Timng (IDT
Standard and FWFT Mode)
.
HALF-FULL FLAG (
HF
)
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets
HF
LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets
HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS
or
PRS
),
HF
will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192
for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695,
65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for
the IDT72T36125.
In FWFT mode, if no reads are performed after reset (
MRS
or
PRS
),
HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for
the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
See Figure 27,
Half-Full Flag Timng (IDT Standard and FWFT Modes)
,
for the relevant timng information. Because
HF
is updated by both RCLK and
WCLK, it is considered asynchronous.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T36115L7BBI | SWITCH ROLLER LEVER |
| IDT72T36125L7BBI | SWITCH ROLLER LEVER |
| IDT72T3655L6BB | 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS |
| IDT72T3685L6BB | 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS |
| IDT72T3695L6BB | 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS |
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