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| 型號(hào)： | IDT72T51233L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 32K X 18 OTHER FIFO, 3.6 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 25/55頁 |
| 文件大小： | 544K |
| 代理商： | IDT72T51233L5BB |
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IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PAF
n FLAG BUS OPERATION
The IDT72T51233/72T51243/72T51253 multi-queue flow-control devices
can be configured for up to 4 queues, each queue having its own almost full
status. An active queue has its flag status output to the discrete flags,
FF
and
PAF
,
on the write port. Queues that are not selected for a write operation can have
their
PAF
status monitored via the
PAF
n bus. The
PAF
n flag bus is 4 bits wide,
so that all 4 queues can have their status output to the bus. When a single multi-
queue device is used anywhere from1 to 4 queues may be set-up within the
part, each queue having its own dedicated
PAF
flag output on the
PAF
n bus.
Queues 1 through 4 have their
PAF
status to
PAF
[0] through
PAF
[3]
respectively. If less than 4 queues are used then only the associated
PAF
n
outputs will be required, unused
PAF
n outputs will be dont care outputs. When
devices are connected in expansion mode the
PAF
n flag bus can also be expanded
beyond 4 bits to produce a wider
PAF
n bus that encompasses all queues.
Alternatively, the 4 bit
PAF
n flag bus of each device can be connected together
to forma single 4 bit bus, i.e.
PAF
[0] of device 1 will connect to
PAF
[0] of device
2 etc. When connecting devices in this manner the
PAF
n can only be driven
by a single device at any time, (the
PAF
n outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determned by the state of the FM(flag Mode) input
during a Master Reset.
PAF
n BUS EXPANSION - DIRECT MODE
If FMis LOW at Master Reset then the
PAF
n bus operates in Direct
(addressed) mode. In direct mode the user can address the device they require
to control the
PAF
n bus. The address present on the 3 most significant bits of
the WRADD[4:0] address bus with FSTR (
PAF
flag strobe), HIGH will be
selected as the device on a rising edge of WCLK. So to address the first device
in a bank of devices the WRADD[4:0] address should be “000xx” the second
device “001xx” and so on. The 3 most significant bits of the WRADD[4:0] address
bus correspond to the device ID inputs ID[2:0]. The
PAF
n bus will change status
to show the new device selected 1 WCLK cycle after device selection. Note, that
if a read or write operation is occurring to a specific queue, say queue ‘x’ on
the same cycle as a
PAF
n bus switch to the device containing queue x’, then
there may be an extra WCLK cycle delay before that queues status is correctly
shown on the respective output of the
PAF
n bus. However, the “active”
PAF
flag will show correct status at all times.
Devices can be selected on consecutive WCLK cycles, that is the device
controlling the
PAF
n bus can change every WCLK cycle. Also, data present on
the input bus, Din, can be written into a queue on the same WLCK rising edge
that a device is being selected on the
PAF
n bus, the only restriction being that
a write queue selection and
PAF
n bus selection cannot be made on the same
cycle.
PAF
n – POLLED BUS
If FMis HIGH at Master Reset then the
PAF
n bus operates in Polled (Looped)
mode. In polled mode the
PAF
n bus automatically cycles through the devices
connected in expansion. In expansion mode one device will be set as the
Master, MAST input tied HIGH, all other devices will have MAST tied LOW. The
master device is the first device to take control of the
PAF
n bus and place the
PAF
status of its queues onto the bus on the first rising edge of WCLK after the
MRS
input goes HIGH once a Master Reset is complete. The FSYNC (
PAF
sync
pulse) output of the first device (master device), will be HIGH for one cycle of
WCLK indicating that it is has control of the
PAF
n bus for that cycle.
The device also passes a “token” onto the next device in the chain, the next
device assumng control of the
PAF
n bus on the next WCLK cycle. This token
passing is done via the FXO outputs and FXI inputs of the devices (“
PAF
n
Expansion Out” and “
PAF
n Expansion In”). The FXO output of the first device
connecting to the FXI input of the second device in the chain, the FXO of the
second device connects to the FXI of the third device and so on. The FXO of
the final device in a chain connects to the FXI of the first device, so that once the
PAF
n bus has cycled through all devices control is again passed to the first
device. The FXO output of a device will be HIGH for the WCLK cycle it has control
of the bus.
Please refer to Figure 26,
PAF
n Bus – Polled Mode
for timng information.
PAE
n FLAG BUS OPERATION
The IDT72T51233/72T51243/72T51253 multi-queue flow-control de-
vices can be configured for up to 4 queues, each queue having its own almost
empty status. An active queue has its flag status output to the discrete flags,
OV
and
PAE
, on the read port. Queues that are not selected for a read operation
can have their
PAE
status monitored via the
PAE
n bus. The
PAE
n flag bus is
4 bits wide, so that all 4 queues can have their status output to the bus. The
multi-queue device can provide “Almost Empty” status via the
PAE
n bus
of its queues. If it is LOW then the
PAE
n bus will provide “Almost Empty”
status.
When a single multi-queue device is used anywhere from1 to 4 queues may
be set-up within the part, each queue having its own dedicated
PAE
n flag output
on the
PAE
n bus. Queues 1 through 4 have their
PAE
status to
PAE
[0] through
PAE
[3] respectively. If less than 4 queues are used then only the associated
PAE
n outputs will be required, unused
PAE
n outputs will be dont care outputs.
When devices are connected in expansion mode the
PAE
n flag bus can also
be expanded beyond 4 bits to produce a wider
PAE
n bus that encompasses
all queues.
Alternatively, the 4 bit
PAE
n flag bus of each device can be connected
together to forma single 4 bit bus, i.e.
PAE
[0] of device 1 will connect to
PAE
[0]
of device 2 etc. When connecting devices in this manner the
PAE
n bus can only
be driven by a single device at any time, (the
PAE
n outputs of all other devices
must be in high impedance state). There are two methods by which the user
can select which device has control of the bus, these are “Direct” (Addressed)
mode or “Polled” (Looped) mode, determned by the state of the FM(flag Mode)
input during a Master Reset.
PAE
n - DIRECT BUS
If FMis LOW at Master Reset then the
PAE
n bus operates in Direct
(addressed) mode. In direct mode the user can address the device they require
to control the
PAE
n bus. The address present on the 3 most significant bits of
the RDADD[4:0] address bus with ESTR (
PAE
flag strobe), HIGH will be
selected as the device on a rising edge of RCLK. So to address the first device
in a bank of devices the RDADD[4:0] address should be “000xx” the second
device “001xx” and so on. The 3 most significant bits of the RDADD[5:0] address
bus correspond to the device ID inputs ID[2:0]. The
PAE
n bus will change status
to show the new device selected 1 RCLK cycle after device selection. Note, that
if a read or write operation is occurring to a specific queue, say queue ‘x’ on
the same cycle as a
PAE
n bus switch to the device containing queue x’, then
there may be an extra RCLK cycle delay before that queues status is correctly
shown on the respective output of the
PAE
n bus. However, the “active”
PAE
flag will show correct status at all times.
Devices can be selected on consecutive RCLK cycles, that is the device
controlling the
PAE
n bus can change every RCLK cycle. Also, data can be read
out of a queue on the same RCLK rising edge that a device is being selected
on the
PAE
n bus, the only restriction being that a read queue selection and
PAE
n
bus selection cannot be made on the same cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51233L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51243 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51243L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T51248L5BB | 功能描述:IC FIFO 4KX8 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51248L6-7BB | 功能描述:IC FIFO 4KX8 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51248L6-7BBI | 功能描述:IC FIFO 4KX8 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L5BB | 功能描述:IC FIFO 327768X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BB | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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