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參數(shù)資料
| 型號： | IDT72T51233L5BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 2.5V的多隊(duì)列流量控制器件（32隊(duì)列）36位寬度的配置1179648位和2359296位 |
| 文件頁數(shù)： | 7/55頁 |
| 文件大小： | 544K |
| 代理商： | IDT72T51233L5BBI |
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IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
FSTR
(R4)
PAF
n Flag Bus
Strobe
LVTTL
INPUT
If direct operation of the
PAF
n bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a device for its queues to be placed on to the
PAF
n bus outputs. A device
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a
PAF
n flag bus
selection cannot be made, (FSTR must NOT go active) until programmng of the part has been completed
and
SENO
has gone LOW.
FSYNC is an output fromthe multi-queue device that provides a synchronizing pulse for the
PAF
n bus
during Polled operation of the
PAF
n bus. During Polled operation each device's queue status flags
are loaded on to the
PAF
n bus outputs sequentially based on WCLK. The first WCLK rising edge loads
device 1 onto
PAF
n, the second WCLK rising edge loads device 2 and so on. During the WCLK cycle
that a selected device is placed on to the
PAF
n bus, the FSYNC output will be HIGH.
The FXI input is used when multi-queue devices are connected in expansion mode and Polled
PAF
n
bus operation has been selected . FXI of device ‘N connects directly to FXO of device ‘N-1’. The FXI
receives a token fromthe previous device in a chain. In single device mode the FXI input must be tied
LOW if the
PAF
n bus is operated in direct mode. If the
PAF
n bus is operated in polled mode the FXI input
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAF
n bus operation has been selected . FXO of device N connects directly to FXI of device N+1’. This
pin pulses when device N places its
PAE
status on to the
PAF
n bus with respect to WCLK. This pulse
(token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the
first quadrant of device N+1 will be loaded on to the
PAF
n bus. This continues through the chain and FXO
of the last device is then looped back to FXI of the first device. The FSYNC output of each device in the
chain provides synchronization to the user of this looping event.
HSTL-LVTTL For the 4Q multi-queue device the WRADD and RDADD address busses are 5 bits wide. When a queue
INPUT
selection takes place the 3 MSbs of this 5 bit address bus are used to address the specific device (the
2 LSbs are used to address the queue within that device). During write/read operations the 3 MSbs
of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is 111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as 000’ and the 3 MSbs of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master does not have to have the ID of ‘000’.
LVTTL
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
INPUT
required then IOSEL should be tied HIGH. If LVTTL I/O are required then it should be tied LOW.
LVTTL
IW selects the bus width for the data input bus. If IW is LOW during a Master Reset then the bus width
INPUT
is x18, if HIGH then it is x9.
HSTL-LVTTL The state of this input at Master Reset determnes whether a given device (within a chain of devices), is the
INPUT
Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The
master device is the first to take control of all outputs after a master reset, all slave devices go to High-
Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this
pin must be set HIGH.
HSTL-LVTTL A master reset is performed by taking
MRS
fromHIGH to LOW, to HIGH. Device programmng is required
INPUT
after master reset.
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT
and RADEN address bus to address the Null-Q.
HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
INPUT
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the
OE
input is LOW. If
OE
is HIGH then the Qout data outputs will be
FSYNC
(R3)
PAF
n Bus Sync
LVTTL
OUTPUT
FXI
(T2)
PAF
n Bus
Expansion In
LVTTL
INPUT
FXO
(T3)
PAF
n Bus
Expansion Out
LVTTL
OUTPUT
ID[2:0]
(1)
ID2-C9
ID1-A10
ID0-B10
Device ID Pins
IOSEL
(C8)
IW
(1)
(L15)
MAST
(1)
(K15)
IO Select
Input Width
Master Device
MRS
(T9)
NULL-Q
(J2)
OE
(M14)
Master Reset
Null Queue
Select
Output Enable
Symbol &
Pin No.
Name
I/O TYPE
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51233L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51243 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51243L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51243L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
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參數(shù)描述 |
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| IDT72T51248L6-7BBI | 功能描述:IC FIFO 4KX8 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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