參數(shù)資料
型號(hào)： IDT72T51243
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述： 2.5V的多隊(duì)列流量控制器件（32隊(duì)列）36位寬度的配置1179648位和2359296位
文件頁(yè)數(shù)： 19/55頁(yè)
文件大小： 544K
代理商： IDT72T51243
19
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
READ QUEUE SELECTION & READ OPERATION
The multi-queue flow-control devices has up to 4 queues that data is read
fromvia a common read port using the data outputs, Qout, read clock, RCLK
and read enable,
REN
. An output enable,
OE
control pin is also provided to allow
High-Impedance selection of the Qout data outputs. The multi-queue device
read port operates in a mode simlar to “First Word Fall Through” on a traditional
IDT FIFO, but with the added feature of data output pipelining. This data
pipelining on the output port allows the user to achieve 100% bus utilization,
which is the ability to read out a data word on every rising edge of RCLK
regardless of whether a new queue is being selected for read operations.
The queue address present on the read address bus, RDADD during a rising
edge on RCLK while read address enable, RADEN is HIGH, is the queue
selected for read operations. A queue to be read fromneed only be selected
on a single rising edge of RCLK. All subsequent reads will be read fromthat
queue until a new queue is selected. A mnimumof 3 RCLK cycles must occur
between queue selections on the read port. Data fromthe newly selected queue
will be present on the Qout outputs after 3 RCLK cycles plus an access time,
provided that
OE
is active, LOW. On the same RCLK rising edge that the new
queue is selected, data can still be read fromthe previously selected queue,
provided that
REN
is LOW, active and the previous queue is not empty on the
following rising edge of RCLK a word will be read fromthe previously selected
queue regardless of
REN
due to the fall through operation, (provided the queue
is not empty). Remember that
OE
allows the user to place the Qout, data output
bus into High-Impedance and the data can be read onto the output register
regardless of
OE
.
When a queue is selected on the read port, the next word available in that
queue (provided that the queue is not empty), will fall through to the output
register after 3 RCLK cycles. As mentioned, in the previous 3 RCLK cycles to
the new data being available, data can still be read fromthe previous queue,
provided that the queue is not empty. At the point of queue selection, the internal
data pipeline is loaded with the last word fromthe previous queue and the next
word fromthe new queue, both these words will fall through to the output register
consecutively upon selection of the new queue. This pipelining effect provides
the user with 100% bus utilization, and brings about the possibility that a “NULL”
queue may be required within a multi-queue device. Null queue operation is
discussed in the next section on.
If an empty queue is selected for read operations on the rising edge of RCLK,
on the same RCLK edge and the following RCLK edge, 2 final reads will be made
fromthe previous queue, provided that
REN
is active, LOW. On the next RCLK
rising edge a read fromthe new queue will not occur, because the queue is
empty. The last word in the data output register (fromthe previous queue), will
remain there, but the output valid flag,
OV
will go HIGH, to indicate that the data
present is no longer valid.
The RDADD bus is also used in conjunction with ESTR (almost empty flag
bus strobe), to address the almost empty flag bus quadrant during direct mode
of operation. In the 4 queue multi-queue device the RDADD address bus is 5
bits wide. The least significant 2 bits are used to address one of the 4 available
queues within a single multi-queue device. The most significant 3 bits are used
when a device is connected in expansion mode, up to 8 devices can be
connected in expansion, each device having its own 3 bit address. The selected
device is the one for which the address matches a 3 bit ID code, which is statically
setup on the ID pins, ID0, ID1, and ID2 of each individual device.
Refer to Table 2, for Read Address bus arrangement. Also, refer to Figures
13,15 & 16 for read queue selection and read port operation timng diagrams.
Operation RCLK
RADEN
ESTR
RDADD[4:0]
Read Queue
Select
1
0
0
1
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(2 bits = 4 Queues)
4
3
2
1 0
4
3
2
1
X
0
X
Device Select
(Compared to
ID0,1,2)
PAE
n Flag
Bus Device
Select
6115 drw06
Null-Q
0
0
1
0
4
X
3
X
2
X
X
X
Null Queue
Select
1
1
0
TABLE 2 — READ ADDRESS BUS, RDADD[4:0]
相關(guān)PDF資料
PDF描述
IDT72T51243L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51243L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51243L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51243L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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