參數(shù)資料
型號(hào)： IDT72T51243L5BBI
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述： 2.5V的多隊(duì)列流量控制器件（32隊(duì)列）36位寬度的配置1179648位和2359296位
文件頁(yè)數(shù)： 24/55頁(yè)
文件大?。?/td> 544K
代理商： IDT72T51243L5BBI
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE
n Timing
Assertion:
Read Operation to
PAE
n LOW: 2 RCLK*+ t
PAE
De-assertion: Write to
PAE
n HIGH: t
SKEW3
+ RCLK*+ t
PAE
If t
SKEW3
is violated there may be 1 added clock: t
SKEW3
+ 2 RCLK* + t
PAE
*If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
Programmable Almost Empty Flag Bus,
PAE
n Boundary
I/O Set-Up
In18 to out18 or In9 to out9
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
In18 to out18 or In9 to out9
(Write port only selected for same queue when the n+1 Writes
1
st
Word is written in until the boundary is reached) (see note below for timng)
In18 to out9
PAE
n Boundary Condition
PAE
n Goes HIGH after
n+2 Writes
(see note below for timng)
PAE
n Goes HIGH after
PAE
n Goes HIGH after n+1
Writes (see below for timng)
PAE
n Goes HIGH after
([n+2] x 2) Writes
(see note below for timng)
PAE
n Goes HIGH after
In9 to out18
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
In9 to out18
(Write port only selected for same queue when the ([n+1] x 2) Writes
1
st
Word is written in until the boundary is reached) (see note below for timng)
NOTE:
n = Almost Empty Offset value.
Default values:
if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE
Timing
Assertion:
De-assertion: Write to
PAE
HIGH: t
SKEW2
+ RCLK + t
RAE
If t
SKEW2
is violated there may be 1 added clock: t
SKEW2
+ 2 RCLK + t
RAE
Read Operation to
PAE
LOW: 2 RCLK + t
RAE
Programmable Almost Empty Flag,
PAE
Boundary
I/O Set-Up
In18 to out18 or In9 to out9
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
In18 to out9
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
In9 to out18
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
PAE
Assertion
PAE
Goes HIGH after n+2
Writes
(see note below for timng)
PAE
Goes HIGH after n+1
Writes
(see note below for timng)
PAE
Goes HIGH after
([n+2] x 2) Writes
(see note below for timng)
相關(guān)PDF資料
PDF描述
IDT72T51243L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51243L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T54262L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
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