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| 型號： | IDT72T51243L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 64K X 18 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 20/55頁 |
| 文件大?。?/td> | 544K |
| 代理商： | IDT72T51243L6BBI |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
NULL QUEUE OPERATION (OF THE READ PORT)
Pipelining of data to the output port enables the device to provide 100% bus
utilization in standard mode. Data can be read out of the multi-queue flow-control
device on every RCLK cycle regardless of queue switches or other operations.
The device architecture is such that the pipeline is constantly filled with the next
words in a selected queue to be read out, again providing 100% bus utilization.
This type of architecture does assume that the user is constantly switching
queues such that during a queue switch, the last data word required fromthe
previous queue will fall through the pipeline to the output.
Note, that if reads cease at the empty boundary of a queue, then the last word
will automatically flow through the pipeline to the output.
The Null Q operation is achieved by setting the Null Q signal HIGH during
a queue select. Note that the read address bus RDADD[4:0] is a don't care. The
Null Queue is a separate queue within the device and thus the maximumnumber
of queues and memory is always available regardless of whether or not the Null
queue is used. Also note that in expansion mode a user may want to use a
dedicated null queue for each device. A null queue can be selected when no
further reads are required froma previously selected queue. Changing to a null
queue will continue to propagate data in the pipeline to the previous queue's
output. The Null Q can remain selected until a data becomes available in another
queue for reading. The Null-Q can be utilized in either standard or packet mode.
Note: If the user switches the read port to the null queue, this queue is seen
as and treated as an empty queue, therefore after switching to the null queue
the last word fromthe previous queue will remain in the output register and the
OV
flag will go HIGH, indicating data is not valid.
The Null queue operation only has significance to the read port of the multi-
queue, it is a means to force data through the pipeline to the output. Null Q
selection and operation has no meaning on the write port of the device. Also,
refer to Figure 17,
Read Operation and Null Queue Select
for diagram
BUS MATCHING OPERATION
Bus Matching operation between the input port and output port is available.
During a master reset of the multi-queue the state of the two setup pins, IW (Input
Width) and OW (Output Width) determne the input and output port bus widths
as per the selections shown in Table 3, “Bus Matching Set-up”. 9 bit bytes or
18 bit words can be written into and read formthe queues. When writing to or
reading fromthe multi-queue in a bus matching mode, the device orders data in
a “Little Endian” format. See Figure 3,
Bus Matching Byte Arrangement
for details.
The Full flag and Almost Full flag operation is always based on writes and
reads of data widths determned by the write port width. For example, if the input
port is x18 and the output port is x9, then two data reads froma full queue will
be required to cause the full flag to go HIGH (queue not full). Conversely, the
Output Valid flag and Almost Empty flag operations are always based on writes
and reads of data widths determned by the read port. For example, if the input port
is x9 and the output port is x18, two write operations will be required to cause the
output valid flag of an empty queue to go LOW, output valid (queue is not empty).
Note, that the input port serves all queues within a device, as does the output
port, therefore the input bus width to all queues is equal (determned by the input
port size) and the output bus width fromall queues is equal (determned by the
output port size).
TABLE 3
—
BUS-MATCHING SET-UP
IW
OW
0
0
0
1
1
0
1
1
FULL FLAG OPERATION
The multi-queue flow-control devices provides a single Full Flag output,
FF
.
The
FF
flag output provides a full status of the queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the full condition of all queues within it, however
only the queue that is selected for write operations has its full status output to the
FF
flag. This dedicated flag is often referred to as the “active queue full flag”.
When queue switches are being made on the write port, the
FF
flag output
will switch to the new queue and provide the user with the new queue status,
on the cycle after a new queue selection is made. The user then has a full status
for the new queue one cycle ahead of the WCLK rising edge that data can be
written into the new queue. That is, a new queue can be selected on the write
port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the
second rising edge of WCLK, the
FF
flag output will show the full status of the
newly selected queue. On the third rising edge of WCLK following the queue
selection, data can be written into the newly selected queue provided that data
and enable setup & hold times are met.
Note, the
FF
flag will provide status of a newly selected queue two WCLK cycle
after queue selection, which is one cycle before data can be written to that queue.
This prevents the user fromwriting data to a queue that is full, (assumng that
a queue switch has been made to a queue that is actually full).
The
FF
flag is synchronous to the WCLK and all transitions of the
FF
flag occur
based on a rising edge of WCLK. Internally the multi-queue device monitors and
keeps a record of the full status for all queues. It is possible that the status of a
FF
flag maybe changing internally even though that flag is not the active queue
flag (selected on the write port). A queue selected on the read port may
experience a change of its internal full flag status based on read operations.
See Figure 10,
Write Queue Select, Write Operation and Full Flag
Operation in Single Device Mode
and Figure 12,
Full Flag Timng in Expansion
Mode
for timng information.
EXPANSION MODE - FULL FLAG OPERATION
When multi-queue devices are connected in Expansion mode the
FF
flags
of all devices should be connected together, such that a systemcontroller
monitoring and managing the multi-queue devices write port only looks at a
single
FF
flag (as opposed to a discrete
FF
flag for each device). This
FF
flag
is only pertinent to the queue being selected for write operations at that time.
Remember, that when in expansion mode only one multi-queue device can be
written to at any moment in time, thus the
FF
flag provides status of the active
queue on the write port.
This connection of flag outputs to create a single flag requires that the
FF
flag
output have a High-Impedance capability, such that when a queue selection is
made only a single device drives the
FF
flag bus and all other
FF
flag outputs
connected to the
FF
flag bus are placed into High-Impedance. The user does
not have to select this High-Impedance state, a given multi-queue flow-control
devices will automatically place its
FF
flag output into High-Impedance when
none of its queues are selected for write operations.
When queues within a single device are selected for write operations, the
FF
flag output of that device will maintain control of the
FF
flag bus. Its
FF
flag will
simply update between queue switches to show the respective queue full status.
The multi-queue device places its
FF
flag output into High-Impedance based
on the 3 bit ID code found in the 3 most significant bits of the write queue address
bus, WRADD. If the 3 most significant bits of WRADD match the 3 bit ID code setup
on the static inputs, ID0, ID1 and ID2 then the
FF
flag output of the respective
device will be in a Low-Impedance state. If they do not match, then the
FF
flag
output of the respective device will be in a High-Impedance state. See Figure
12,
Full Flag Timng in Expansion Mode
for details of flag operation, including
when more than one device is connected in expansion.
Write Port
x18
x18
x9
x9
Read Port
x18
x9
x18
x9
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參數(shù)描述 |
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| IDT72T51248L5BB | 功能描述:IC FIFO 4KX8 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51248L6-7BB | 功能描述:IC FIFO 4KX8 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51248L6-7BBI | 功能描述:IC FIFO 4KX8 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L5BB | 功能描述:IC FIFO 327768X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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