參數(shù)資料
型號： IDT72T51253
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述： 2.5V的多隊列流量控制器件（32隊列）36位寬度的配置1179648位和2359296位
文件頁數(shù)： 44/55頁
文件大?。?/td> 544K
代理商： IDT72T51253
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
Dn
Prev
PAE
n
RCLK
Device 5
101 xx
t
AH
1
t
RAE
Device 5
Device 5
t
PAEHZ
t
PAEZL
xxxx1xxx
xxxx1xxx
t
SKEW3
xxxx1xxx
Device 5
2
t
STH
t
PAE
6115 drw28
t
RAE
*DD*
*EE*
*GG*
*FF*
xxxx1xxx
Device 5
t
ENH
t
ENS
Wy
D5 Q3
Wy+1
D5 Q3
Wy+3
D5 Q3
Wy+2
D5 Q3
Wa+1
D5 QP
t
A
t
A
t
A
t
A
t
DH
D3Q2
011 10
Wn
D5 Q3
Wn+1
D5Q3
Device 4
100 xx
*D*
3
*E*
*F*
*G*
t
QH
t
QS
t
AH
t
AS
t
AH
t
AS
t
ENH
t
STH
t
STS
t
ENS
t
ENH
t
RAE
D5 Q3
status
ESTR
RDADD
100 11
D5Q3
t
AS
t
AH
t
AS
Previous value loaded on to PAE bus
RADEN
t
QH
t
QS
t
STS
Device 5
PAE
*AA*
*BB*
D5 QP Status
Bus
PAE
n
Previous value loaded on to PAE bus
REN
Device 5 -Qn
t
A
Wa
D5 QP
t
DS
WEN
WADEN
FSTR
t
AH
100 11
t
AS
WRADD
D5Q3
*A*
*B*
1
t
QH
t
QS
t
ENS
Device 5
PAE
n
Wp+1
Wp
Writes to Previous Q
t
DH
t
DS
t
DH
*C*
2
t
QH
t
QS
*H*
Wp+2
t
DS
Wx
D3 Q2
*CC*
3
1
2
3
Figure 24.
PAE
n - Direct Mode, Flag Operation
Cycle:
*A*
Q3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA*
Q3 of Device 5 is selected for read operations.
A quadrant fromanother device has control of the
PAE
n bus.
The discrete
PAE
output of device 5 is currently in High-Impedance and the
PAE
active flag is controlled by the previously selected device.
*B*
Word Wp+1 is written into the previously selected queue.
*BB*
Current Word is kept on the output bus since
REN
is HIGH.
*C*
Word Wp+2 is written into the previously selected queue.
*CC*
Word Wa+1 of Device 5 Qp is read due to FWFT.
*D*
Word, Wn is written into the newly selected queue, Q3 of Device 5. This write will cause the
PAE
flag on the read port to go fromLOW to HIGH (not almost empty) after time,
t
SKEW3
+ RCLK + t
RAE
(if t
SKEW3
is violated one extra RCLK cycle will be added).
*DD*
Word, Wy fromthe newly selected queue, Q3 will be read out due to FWFT operation.
Device 5 is selected on the
PAE
n bus. Q3 of Device 5 will therefore have is
PAE
status output on
PAE
[0]. There is a single RCLK cycle latency before the
PAE
n bus changes
to the new selection.
*E*
Q2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of Device 5.
*EE*
Word, Wy+1 is read fromQ3 of Device 5.
*F*
No writes occur.
*FF*
Word, Wy+2 is read fromQ3 of Device 5.
The
PAE
n bus changes control to Device 5, the
PAE
n outputs of Device 5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously
selected quadrant now places its
PAE
n outputs into High-Impedance to prevent bus contention.
The discrete
PAE
flag will go HIGH to show that Q3 of Device 5 is not almost empty. Q3 of Device 5 will have its
PAE
status output on
PAE
[0].
*G*
Device 4 is selected on the write port for the
PAF
n bus.
*GG*
The
PAE
n bus updates to show that Q3 of Device 5 is almost empty based on the reading out of word, Wy+1.
The discrete
PAE
flag goes LOW to show that Q3 of Device 5 is almost empty based on the reading of Wy+1.
*H*
Word, Wx is written into Q2 of Device 3.
相關PDF資料
PDF描述
IDT72T51253L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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IDT72T54242L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
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