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參數(shù)資料
| 型號： | IDT72T51253L6BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 128K X 18 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 17/55頁 |
| 文件大?。?/td> | 544K |
| 代理商： | IDT72T51253L6BB |
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17
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
MASTER RESET
A Master Reset is performed by toggling the
MRS
input fromHIGH to LOW
to HIGH. During a master reset all internal multi-queue device setup and control
registers are initialized and require programmng either serially by the user via
the serial port, or using the default settings. During a master reset the state of
the following inputs determne the functionality of the part, these pins should be
held HIGH or LOW.
FM– Flag bus Mode
IW, OW – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
DFM– Programmng mode, serial or default
DF – Offset value for
PAE
and
PAF
Once a master reset has taken place, the device must be programmed either
serially or via the default method before any read/write operations can begin.
See Figure 5,
Master Reset
for relevant timng.
PARTIAL RESET
A Partial Reset is a means by which the user can reset both the read and write
pointers of a single queue that has been setup within a multi-queue device.
Before a partial reset can take place on a queue, the respective queue must be
selected on both the read port and write port a mnimumof 2 RCLK and 2 WCLK
cycles before the
PRS
goes LOW. The partial reset is then performed by toggling
the
PRS
input fromHIGH to LOW to HIGH, maintaining the LOW state for at least
one WCLK and one RCLK cycle. Once a partial reset has taken place a mnimum
of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can
occur.
A Partial Reset only resets the read and write pointers of a given queue, a
partial reset will not effect the overall configuration and setup of the multi-queue
device and its queues.
See Figure 6,
Partial Reset
for relevant timng.
SERIAL PROGRAMMING
The multi-queue flow-control devices is a fully programmable device,
providing the user with flexibility in how queues are configured in terms of the
number of queues, depth of each queue and position of the
PAF
/
PAE
flags within
respective queues. All user programmng is done via the serial port after a master
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and
PAE
/
PAF
offset values. The
IDT72T51233/72T51243/72T51253 devices are capable of up to 4 queues
and therefore contain 4 sets of registers for the setup of each queue.
During a Master Reset if the DFM(Default Mode) input is LOW, then the device
will require serial programmng by the user. It is recommended that the user
utilize a C’ programprovided by IDT, this programwill prompt the user for all
information regarding the multi-queue setup. The programwill then generate
a serial bit streamwhich should be serially loaded into the device via the serial
port. For the IDT72T51233/72T51243/72T51253 devices the serial program-
mng requires a total number of serially loaded bits per device, (SCLK cycles with
SENI
enabled), calculated by: 19+(Qx72) where Q is the number of queues the
user wishes to setup within the device.
Once the master reset is complete and
MRS
is HIGH, the device can be
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that
SENI
(serial in
enable), is LOW. Once serial programmng of the device has been successfully
completed the device will indicate this via the
SENO
(serial output enable) going
active, LOW. Upon detection of completion of programmng, the user should
cease all programmng and take
SENI
inactive, HIGH. Note,
SENO
follows
SENI
once programmng of a device is complete. Therefore,
SENO
will go LOW after
programmng provided
SENI
is LOW, once
SENI
is taken HIGH again,
SENO
will also go HIGH. The operation of the SO output is simlar, when programmng
of a given device is complete, the SO output will follow the SI input.
If devices are being used in expansion mode the serial ports of devices should
be cascaded. The user can load all devices via the serial input port control pins,
SI &
SENI
, of the first device in the chain. Again, the user may utilize the ‘C’
programto generate the serial bit stream the programprompting the user for
the number of devices to be programmed. The
SENO
and SO (serial out) of
the first device should be connected to the
SENI
and SI inputs of the second
device respectively and so on, with the
SENO
& SO outputs connecting to the
SENI
& SI inputs of all devices through the chain. All devices in the chain should
be connected to a common SCLK. The serial output port of the final device should
be monitored by the user. When
SENO
of the final device goes LOW, this
indicates that serial programmng of all devices has been successfully com-
pleted. Upon detection of completion of programmng, the user should cease all
programmng and take
SENI
of the first device in the chain inactive, HIGH.
As mentioned, the first device in the chain has its serial input port controlled
by the user, this is the first device to have its internal registers serially loaded
by the serial bit stream When programmng of this device is complete it will take
its
SENO
output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data fromthe SO of the first device, while the second device has its
SENI
input LOW. This process continues through the chain until all devices are
programmed and the
SENO
of the final device goes LOW.
Once all serial programmng has been successfully completed, normal
operations, (queue selections on the read and write ports) may begin. When
connected in expansion mode, the IDT72T51233/72T51243/72T51253 de-
vices require a total number of serially loaded bits per device to complete serial
programmng, (SCLK cycles with
SENI
enabled), calculated by: n[19+(Qx72)]
where Q is the number of queues the user wishes to setup within the device,
where n is the number of devices in the chain.
See Figure 7,
Serial Port Connection
and Figure 8,
Serial Programmng
for
connection and timng information.
DEFAULT PROGRAMMING
During a Master Reset if the DFM(Default Mode) input is HIGH the multi-
queue device will be configured for default programmng, (serial programmng
is not permtted). Default programmng provides the user with a simpler,
however limted means by which to setup the multi-queue flow-control devices,
rather than using the serial programmng method. The default mode will
configure a multi-queue device such that the maximumnumber of queues
possible are setup, with all of the parts available memory blocks being allocated
equally between the queues. The values of the
PAE
/
PAF
offsets is determned
by the state of the DF (default) pin during a master reset.
For the IDT72T51233/72T51243/72T51253 devices the default mode will
setup 4 queues, each queue configured as follows: For the IDT72T51233 with
x9 input and x9 output ports, 16,384 x 9. If one or both ports is x18, 8,192 x
18. For the IDT72T51243 with x9 input and x9 output ports, 32,768 x 9. If one
or both ports is x18, 16,384 x 18. For the IDT72T51253 with x9 input and x9
output ports, 65,536 x 9. If one or both ports is x18, 32,768 x 18. For both devices
the value of the
PAE
/
PAF
offsets is determned at master reset by the state of
the DF input. If DF is LOW then both the
PAE
&
PAF
offset will be 8, if HIGH then
the value is 128.
When configuring the IDT72T51233/72T51243/72T51253 devices in de-
fault mode the user simply has to apply WCLK cycles after a master reset, until
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51233 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T51258L5BB | 功能描述:IC FIFO 327768X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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