參數(shù)資料
型號： IDT72T6360L7-5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 46/51頁
文件大小： 508K
代理商： IDT72T6360L7-5BBI
50
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 10, 2005
WIDTH EXPANSION CONFIGURATION
The sequential flow-control (SFC) device can be connected with another
SFCs in width expansion to support bus-widths greater than 36-bits. This
configurationconnectstheinputandoutputbusoftwodevicestogethertocreate
a wider bus. The read and write clocks for each device are driven with a clock
driver. The empty and full flags of both devices are connected to a logic gate
(AND/OR) depending on whether IDT Standard mode or FWFT mode is
selected. Because of the variation in skew between the read clock and write
clock,itispossiblefor
EF/FFdeassertionandIR/ORassertiontovaryfromone
cyclebetweenthedevices. Thelogicgateconnectedtothestatusflagswillcreate
a composite flag that will update the status of both SFC devices to represent a
more accurate status of the configuration. To minimize the skew between the
two write and read clocks, a clock driver (IDT5T905 recommended) is used
to drive the input clocks for both SFC devices. Figure 36 illustrates the width
expansion configuration.
WCLK
WEN
Dn
RCLK
REN
EF/OR
Qn
SFC
FF/IR
Write Clock
Write Enable
Full Flag/Input Ready
Data Inputs
Read Clock
Empty Flag/Output Ready
Read Enable
Data Outputs
64
36
WCLK
WEN
Dn
RCLK
REN
EF/OR
Qn
SFC
FF/IR
Gate
(1)
Full Flag/Input Ready
Gate
(1)
Empty Flag/Output Ready
64
Clock Driver
IDT5T905
Clock Driver
IDT5T905
Write Clock
Read Clock
Clock Driver
IDT5T905
Clock Driver
IDT5T905
36
6357 drw50
Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output signals directly together.
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